L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

5.1.2.3. Deserializer

The deserializer block clocks in serial input data from the receiver buffer using the high-speed serial recovered clock and deserializes the data using the low-speed parallel recovered clock. The deserializer forwards the deserialized data to the receiver PCS or FPGA fabric.

The deserializer supports the following deserialization factors: 8, 10, 16, 20, 32, 40, and 64. The deserializer can be powered down when the CDR acts as a CMU.

Figure 195. Deserializer Block Diagram The deserializer block sends out the LSB of the input data first.

Did you find the information on this page useful?

Characters remaining:

Feedback Message