L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

A.1. ATX_PLL Logical Register Map

Stratix 10 ATX_PLL Register Map Summary

Feature Feature Description
ATX PLL Calibration ATX PLL Calibration allows users to optimize the ATX PLL performance when changing data rates.
Optional Reconfiguration Logic ATX PLL- Capability Enables ATX PLL capabilities to be readable.
Optional Reconfiguration Logic ATX PLL- Control & Status Enables users to read the status of ATX PLL functions and reset the ATX PLL.
Embedded Streamer (ATX PLL)

Enables logic in ATX PLL to store the individual profile information and

perform .mif streaming for reconfiguration application.

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