L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

4.2. Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP Implementation

Figure 172. Reset Controller, Transceiver PHY and TX PLL IP Cores Interaction

Transceiver Reset Endpoints—The Transceiver PHY IP core contains Transceiver Reset Endpoints (TREs). The analog and digital reset ports (both TX/RX) of the Transceiver Native PHY IP core are connected to the input of the TX TRE and RX TRE, respectively.

Transceiver Reset Sequencer—The Intel® Quartus® Prime Pro Edition software detects the presence of TREs and automatically inserts only one Transceiver Reset Sequencer (TRS)48. The tx_digitalreset, rx_digitalreset, tx_analogreset and rx_analogreset requests from the reset controller (user-coded or Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP) are received by the TREs. The TRE sends the reset request to the TRS for scheduling. TRS schedules all the requested PCS/PMA resets and provides acknowledgment for each request. You can use either Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP or your own reset controller. However, for the TRS to work correctly, the required timing duration must be followed.

48 There is only one centralized TRS instantiated for one or more Native PHY. The TRS IP is an inferred block and is not visible in the RTL. You have no control over this block.

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