L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

1.3.5.1.1. Transceiver Phase-Locked Loops

Each transceiver channel in Intel® Stratix® 10 devices has direct access to three types of high performance PLLs:

  • Advanced Transmit (ATX) PLL
  • Fractional PLL (fPLL)
  • Channel PLL / Clock Multiplier Unit (CMU) PLL.

These transceiver PLLs along with the Master or Local Clock Generation Blocks (CGB) drive the transceiver channels.

Advanced Transmit (ATX) PLL

The ATX PLL is the transceiver channel’s primary transmit PLL. It can operate over the full range of supported datarates required for high datarate applications. An ATX PLL supports both integer frequency synthesis and coarse resolution fractional frequency synthesis (when configured as a cascade source).

Fractional PLL (fPLL)

A fractional PLL (fPLL) is an alternate transmit PLL used for generating lower clock frequencies for lower datarate applications. fPLLs support both integer frequency synthesis and fine resolution fractional frequency synthesis. Unlike the ATX PLL, you can also use the fPLL to synthesize frequencies that can drive the core through the FPGA fabric clock networks.

Channel PLL (CMU/CDR PLL)

A channel PLL is located within each transceiver channel. The channel's primary function is clock and data recovery in the transceiver channel when you use the PLL in clock data recovery (CDR) mode. You can use the channel PLLs of channel 1 and 4 as transmit PLLs when configured in clock multiplier unit (CMU) mode. You cannot configure the channel PLLs of channel 0, 2, 3, and 5 in CMU mode; therefore, you cannot use them as transmit PLLs. You cannot use the receiver channel when you use it as a Channel PLL/CMU.

Did you find the information on this page useful?

Characters remaining:

Feedback Message