L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.5.3.1. 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with KR FEC Variants

10GBASE-R PHY is the Ethernet-specific physical layer running at a 10.3125-Gbps datarate as defined in Clause 49 of the IEEE 802.3-2008 specification. Intel® Stratix® 10 transceivers can implement 10GBASE-R variants like 10GBASE-R with IEEE 1588v2, and with KR forward error correction (FEC).

The 10GBASE-R parallel data interface is the 10 Gigabit Media Independent Interface (XGMII) that interfaces with the Media Access Control (MAC), which has the optional Reconciliation Sub-layer (RS).

The following 10GBASE-R variants are available from presets:

  • 10GBASE-R
  • 10GBASE-R Low Latency
  • 10GBASE-R 1588
  • 10GBASE-R w/ KR-FEC

Intel recommends that you use the presets for selecting the suitable 10GBASE-R variants directly if you are configuring through the Native PHY IP core.

Figure 126.  Transceiver Channel Datapath and Clocking for 10GBASE-R (PCS-PMA Interface Width = 32 Bits)

10GBASE-R with IEEE 1588v2

The output clock frequency of tx_clkout and rx_clkout to the FPGA fabric is based on the PCS-PMA interface width. For example, if the PCS-PMA interface is 32-bit, tx_clkout and rx_clkout run at 10.3125 Gbps/32-bit = 322.265625 MHz.

The 10GBASE-R PHY with IEEE 1588v2 uses both the TX Core FIFO and the RX Core FIFO in Phase Compensation mode. The effective XGMII data is running at 156.25 MHz interfacing with the MAC layer.

The IEEE 1588 Precision Time Protocol (PTP) is supported by the preset of the Native PHY IP core that configures 10GBASE-R PHY IP in IEEE-1588v2 mode. PTP is used for precise synchronization of clocks in applications such as:

  • Distributed systems in telecommunications
  • Power generation and distribution
  • Industrial automation
  • Robotics
  • Data acquisition
  • Test equipment
  • Measurement

The protocol is applicable to systems communicating by local area networks including, but not limited to, Ethernet. The protocol enables heterogeneous systems that include clocks of various inherent precision, resolution, and stability to synchronize to a grandmaster clock.

Figure 127. Transceiver Channel Datapath and Clocking for 10GBASE-R with IEEE 1588v2 (PCS-PMA Interface Width = 32 Bits)

10GBASE-R with KR-FEC

Intel® Stratix® 10 10GBASE-R has the optional FEC variant that also targets the 10GBASE-KR PHY. This provides a coding gain to increase the link budget and BER performance on a broader set of backplane channels as defined in Clause 69. It provides additional margin to account for variations in manufacturing and environment conditions. The additional TX FEC sublayer:

  • Receives data from the TX PCS
  • Transcodes 64b/66b words
  • Performs encoding/framing
  • Scrambles and sends the FEC data to the PMA

The RX FEC sublayer:

  • Receives data from the PMA
  • Performs descrambling
  • Achieves FEC framing synchronization
  • Decodes and corrects data where necessary and possible
  • Recodes 64b/66b words and sends the data to the PCS

The 10GBASE-R with KR FEC protocol is a KR FEC sublayer placed between the PCS and PMA sublayers of the 10GBASE-R physical layer.

Figure 128. Transceiver Channel Datapath and Clocking for 10GBASE-R with KR FEC (PCS-PMA interface width = 64 bits)

The CMU PLL or the ATX PLLs generate the TX high speed serial clock.

Figure 129. Clock Generation and Distribution for 10GBASE-R with FEC SupportExample using a 64-bit PCS-PMA interface width.

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