L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

3.11. Using PLLs and Clock Networks

For L-Tile and H-Tile, PLLs are not integrated in the Native PHY IP core. You must instantiate the PLL IP cores separately. Unlike in some previous device families, PLL merging is no longer performed by the Intel® Quartus® Prime Pro Edition. This gives you more control, transparency, and flexibility in the design process. You can specify the channel configuration and PLL usage.

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