L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

7.2.1. Avalon® Memory-Mapped Interface Arbitration Registers

Table 167.   Avalon® Memory-Mapped Interface Arbitration Registers
Bit Offset Address Description
[0] 0x0 50 This bit arbitrates the control of the Avalon® memory-mapped interface.
  • Set this bit to 0 to request control of the internal configuration bus by user.
  • Set this bit to 1 to pass the internal configuration bus control to PreSICE.
[1] 0x0 This bit indicates whether or not calibration is done. This is the inverted cal_busy signal. You can write to this bit; however, if you accidentally write 0x0 without enabling any calibration bit in 0x100, PreSICE may not set this bit to 0x1, and cal_busy remains high. Channel reset is triggered if cal_busy is connected to the reset controller.
  • 0x1 = calibration complete
  • 0x0 = calibration not complete. The cal_busy signal is activated two clock cycles after you write 0x0 to this bit.
Note: During calibration when reconfig_waitrequest is high, you can not read offset address 0x0.
50 The transceiver channel, ATX PLL, and fPLL use the same offset address.

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