L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

7.5.9. Recalibrating the ATX PLL

Note: Address refers to the ATX PLL offset address.
  1. Perform a RMW operation on 0x01 with mask 0x01 to address 0x100. This sets the ATX PLL calibration enable bit.
  2. Write 0x01 to address 0x00. This lets the PreSICE perform the calibration.
  3. Loop read 0x480[1] until you see it become 0x0.
    ATX PLL calibration is complete when 0x480[1] = 0x0.

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