L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

5.1.2. Receiver PMA

The receiver recovers the clock information from the received data, deserializes the high-speed serial data and creates a parallel data stream for either the receiver PCS or the FPGA fabric.

The receiver portion of the PMA is comprised of the receiver buffer, the clock data recovery (CDR) unit, and the deserializer.

Figure 188. Receiver PMA Block Diagram
Figure 189. Receiver Buffer

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