L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

A.4.5. Optional Reconfiguration Logic PHY- Capability

Enables Native PHY channels' capabilities to be readable.
Name Address Type Attribute Name Encodings
IP Identifier

0x400

0x401

0x402

0x403

read-only PHYIP_address_id Unique identifier for the Native PHY instance.
Status Register Enabled

0x404[0]

read-only PHYIP_status_register_enable Indicates if the status registers have been enabled. 1'b1 indicates the feature is enabled.
Control Register Enabled

0x405[0]

read-only PHYIP_control_register_enable Indicates if the control registers have been enabled. 1'b1 indicates the feature is enabled.
Number of Channels

0x410[7:0]

read-only PHYIP_chnls Shows the number of channels specified for the Native PHY instance.
Channel Number

0x411[7:0]

read-only PHYIP_chnl_num Shows the unique channel number.
Duplex

0x412[1:0]

read-only PHYIP_duplex

Shows transceiver mode:

2'b00: <unused>

2'b10: TX

2'b01: RX

2'b11: duplex

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