L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

3.3.4. GXT Clock Network

ATX PLLs can access the GXT Clock Network. The clock network allows a single ATX PLL to drive up to 6 GXT channels in non-bonded mode on H-Tile and up to 4 GXT channels in non-bonded mode on L-Tile.

  • Each ATX PLL has a 3:1 mux that can select whether to select its own, above ATX PLL, or below ATX PLL to drive two adjacent GXT channels.
    • Intel® Quartus® Prime Pro Edition does not infer the 3:1 mux based on your design. Instead, you need to instantiate up to 3 ATX PLL IP cores. One instance is configured as a PLL, while the other two instances have the 3:1 mux drop-down set to select the first ATX PLL as the adjacent GXT channels source.
      • Use the additional drop-down to select source based on the device selected in the project.
    • The top ATX PLL in a bank can drive the following GXT channels:
      • Channels 0,1, 3, 4 in the bank
      • Channels 0, 1 in the bank above in the same H-Tile
    • The bottom ATX PLL in a bank can drive the following GXT channels:
      • Channels 0, 1, 3, 4 in the bank
      • Channels 3, 4 in the bank below in the same H-Tile
Figure 154. Top ATX PLL in a Transceiver Bank Driving GXT Channels

Refer also to Figure 143.

Figure 155. Bottom ATX PLL in a Transceiver Bank Driving GXT Channels

Refer also to Figure 143.

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