L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

7.2.2.2. ATX PLL/fPLL/CMU PLL Calibration Registers

During calibration when PreSICE is controlling the internal configuration bus, you cannot read from or write to calibration enable registers.

To enable calibration, you must perform a read-modify-write on offset address 0x100.

  1. Read the offset address 0x100.
  2. Keep the value from MSB[7:1] and set LSB[0] to 1.
  3. Write the new value to the offset address 0x100.
Table 169.  ATX PLL/fPLL/CMU PLL Calibration Enable Registers
Bit TX PLL Calibration Enable Register Offset Address 0x100
0

Set to 1 to enable ATX PLL calibration.

Set to 1 to enable CMU PLL calibration.

1

Set to 1 to enable fPLL calibration.

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