L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

5.2.2.10.2. Register Mode

The register mode bypasses the FIFO functionality to eliminate the FIFO latency uncertainty for applications with stringent latency requirements. This is accomplished by tying the read clock of the FIFO with its write clock. In Register mode, rx_parallel_data (data), rx_control indicates whether rx_parallel_data is a data or control word, and rx_enh_data_valid (data valid) are registered at the FIFO output.

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