L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.3.12. PMA, Calibration, and Reset Ports

This section describes the PMA and calibration ports for the Transceiver Native PHY IP core.

In the following tables, the variables represent these parameters:

  • <n>—The number of lanes
  • <d>—The serialization factor
  • <s>—The symbol size
  • <p>—The number of PLLs
Table 50.  TX PMA Ports
Name Direction Clock Domain Description
tx_serial_data[<n>-1:0] Input N/A

This is the serial data output of the TX PMA.

tx_serial_clk0 Input Clock This is the serial clock from the TX PLL. The frequency of this clock depends on the datarate and clock division factor. This clock is for non bonded channels only. For bonded channels use the tx_bonding_clocks clock TX input.
tx_bonding_clocks[<n><6>-1:0] Input Clock This is a 6-bit bus which carries the low speed parallel clock per channel. These clocks are outputs from the master CGB. Use these clocks for bonded channels only.
Optional Ports
tx_serial_clk1

tx_serial_clk2

tx_serial_clk3

tx_serial_clk4

Inputs Clocks

These are the serial clocks from the TX PLL. These additional ports are enabled when you specify more than one TX PLL.

tx_pma_iqtxrx_clkout Output Clock This port is available if you turn on Enable tx_ pma_iqtxrx_clkout port in the Transceiver Native PHY IP core Parameter Editor. This output clock can be used to cascade the TX PMA output clock to the input of a PLL in the same tile.
tx_pma_elecidle[<n>-1:0] Input Asynchronous

FSR9

When you assert this signal, the transmitter is forced to electrical idle. This port has no effect when you configure the transceiver for the PCI Express protocol.
Table 51.  RX PMA Ports
Name Direction Clock Domain Description
rx_serial_data[<n>-1:0] Input N/A

Specifies serial data input to the RX PMA.

rx_cdr_refclk0 Input Clock

Specifies reference clock input to the RX clock data recovery (CDR) circuitry.

Optional Ports
rx_cdr_refclk1rx_cdr_refclk4 Input Clock

Specifies reference clock inputs to the RX clock data recovery (CDR) circuitry. These ports allow you to change the CDR datarate.

rx_pma_iqtxrx_clkout Output Clock This port is available if you turn on Enable rx_ pma_iqtxrx_clkout port in the Transceiver Native PHY IP core Parameter Editor. This output clock can be used to cascade the RX PMA output clock to the input of a PLL.
rx_pma_clkslip Input Clock

SSR9

When asserted, causes the deserializer to either skip one serial bit or pauses the serial clock for one cycle to achieve word alignment.
rx_is_lockedtodata[<n>-1:0] Output rx_clkout

When asserted, indicates that the CDR PLL is in locked-to-data mode. When continuously asserted and does not switch between asserted and deasserted, you can confirm that it is actually locked to data.

rx_is_lockedtoref[<n>-1:0] Output rx_clkout

When asserted, indicates that the CDR PLL is in locked-to-reference mode.

rx_set_locktodata[<n>-1:0] Input Asynchronous

This port provides manual control of the RX CDR circuitry. When asserted, the CDR switches to the lock-to-data mode. Refer to the Manual Lock Mode section for more details.

rx_set_locktoref[<n>-1:0] Input Asynchronous

This port provides manual control of the RX CDR circuitry. When asserted, the CDR switches to the lock-to-reference mode. Refer to the Manual Lock Mode section for more details.

rx_prbs_done[<n>-1:0] Output rx_coreclkin or rx_clkout

SSR9

When asserted, indicates the verifier has aligned and captured consecutive PRBS patterns and the first pass through a polynomial is complete.

rx_prbs_err[<n>-1:0] Output rx_coreclkin or rx_clkout

SSR9

When asserted, indicates an error only after the rx_prbs_done signal has been asserted. This signal gets asserted for three parallel clock cycles for every error that occurs. Errors can only occur once per word.

rx_prbs_err_clr[<n>-1:0] Input rx_coreclkin or rx_clkout

SSR9

When asserted, clears the PRBS pattern and deasserts the rx_prbs_done signal.
rx_std_signaldetect[<n>-1:0]

Output

Asynchronous

When enabled, the signal threshold detection circuitry senses whether the signal level present at the RX input buffer is above the signal detect threshold voltage. This signal is required and only supports the PCI Express, SATA and SAS protocols.

Table 52.  RX PMA Ports-PMA QPI Options
Name Direction Clock Domain Description
rx_seriallpbken[<n>-1:0] Input

Asynchronous

SSR 10

This port is available if you turn on Enable rx_seriallpbken port in the Transceiver Native PHY IP core Parameter Editor. The assertion of this signal enables the TX to RX serial loopback path within the transceiver. This signal can be enabled in Duplex or Simplex mode. If enabled in Simplex mode, you must drive the signal on both the TX and RX instances from the same source. Otherwise the design fails compilation.
Table 53.  Calibration Status Ports
Name Direction Clock Domain Description
tx_cal_busy[<n>-1:0] Output Asynchronous

SSR9

When asserted, indicates that the initial TX calibration is in progress. For both initial and manual recalibration, this signal is asserted during calibration and deasserts after calibration is completed. You must hold the channel in reset until calibration completes.
rx_cal_busy[<n>-1:0] Output Asynchronous

SSR9

When asserted, indicates that the initial RX calibration is in progress. For both initial and manual recalibration, this signal is asserted during calibration and deasserts after calibration is completed.
Table 54.  Reset Ports
Name Direction Clock Domain11 Description
tx_analogreset[<n>-1:0] Input Asynchronous Resets the PMA TX portion of the transceiver PHY.
tx_digitalreset[<n>-1:0] Input Asynchronous Resets the PCS TX portion of the transceiver PHY.12
rx_analogreset[<n>-1:0] Input Asynchronous Resets the PMA RX portion of the transceiver PHY.
rx_digitalreset[<n>-1:0] Input Asynchronous Resets the PCS RX portion of the transceiver PHY.13
tx_analogreset_stat [<n>-1:0] Output Asynchronous TX PMA reset status port.
rx_analogreset_stat [<n>-1:0] Output Asynchronous RX PMA reset status port.
tx_digitalreset_stat [<n>-1:0] Output Asynchronous TX PCS reset status port.
rx_digitalreset_stat [<n>-1:0] Output Asynchronous RX PCS reset status port.
tx_dll_lock Output Asynchronous TX PCS delay locked loop status port. This port is available when the RX Core FIFO is operating in Interlaken or Basic mode.
Optional Reset Port
rcfg_tx_digitalreset_release_ctrl[<n>-1:0] 14 Input Asynchronous This port usage is mandatory when reconfiguring to or from Enhanced PCS Configurations with TX PCS Gearbox ratios of either 67:32, 67:40, and 67:64.
9 For a detailed description of FSR and SSR signals, please go to the Asynchronous Data Transfer section in the Other Protocols chapter.
10 For a detailed description of FSR and SSR signals, please go to the Asynchronous Data Transfer section in the Other Protocols chapter.
11 Although the reset ports are not synchronous to any clock domain, Intel recommends that you synchronize the reset ports with the system clock.
12 For non-bonded configurations: there is one bit per TX channel. For bonded configurations: there is one bit per PHY instance.
13 For non-bonded configurations: there is one bit per RX channel. For bonded configurations: there is one bit per PHY instance.
14 For rcfg_tx_digitalreset_release_ctrl timing diagrams, refer to the "Special TX PCS Reset Release Sequence" under Resetting Transceiver Channels chapter.

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