L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

A.3.1. fPLL Calibration

fPLL Calibration allows users to optimize the fPLL performance when changing data rates.
Name Address Type Attribute Name Encodings
Internal configuration bus arbitration register for FPLL

0x000[0]

read-write pcs_arbiter_ctrl

This bit arbitrates the control of internal configuration bus.

Write 1'b0 if you want to control the internal configuration bus

Write 1'b1 to pass the internal configuration bus control to PreSICE.

fPLL Calibration Status

0x000[1]

read-write pcs_cal_done

Status for whether or not calibration is done

This is the inverted cal_busy signal.

1'b1: calibration done

1'b0: calibration not done

fPLL calibration enable

0x100[1]

read-write fpll_calibration

fPLL calibration enable

1'b1: fPLL calibration enable on

1'b0: fPLL calibration enable off

Request PreSICE to configure the fPLL in preparation for reconfiguration

0x100[0]

read-write pre_reconfig

Request PreSICE to configure the fPLL in preparation for reconfiguration ENCODINGS:

1'b1: Request PreSICE to configure the PLL in reconfiguration mode

1'b0: Reconfiguration mode not requested

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