L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

4.3.1.6. Special TX PCS Reset Release Sequence

The release of TX PCS reset is handled differently in special cases. To ensure that transmitter channels are ready to transmit, you must properly release the TX PCS reset for these special cases.
While using Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP or while implementing your own reset controller, you must account for the following special cases
  • TX Core FIFO in Interlaken/Basic Mode
  • Double rate transfer mode enabled
    • TX Core FIFO in Phase Compensation Mode
    • TX Core FIFO in Basic Mode

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