L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

5.3.2.6.5. Byte Ordering Register-Transfer Level (RTL)

Intel® Stratix® 10 L-Tile and H-tile devices take advantage of the Standard PCS block to implement sub-10G CPRI and Ethernet protocols.

Figure 219. Byte Ordering in a Duplex Implementation with TX and RX ChannelsBoth channels are configured with the same settings.

The maximum clock speed of the FPGA core limits the FIFO interface. In situations where the FIFO clock speed exceeds the FPGA core clock speed specification, the byte serializer block scales the data width (x2 or x4). The following figure demonstrates the behavior when there is a core clock speed violation.

Figure 220. Byte Ordering with a Core Clock Speed Violation

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