L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 1/30/2024
Document Table of Contents

6.13.2. Optional Reconfiguration Logic

The Intel® Stratix® 10 Transceiver Native PHY, ATX PLL, fPLL, and CMU PLL IP cores contain soft logic for debug purposes known as the Optional Reconfiguration Logic. This soft logic provides a set of registers that enable you to determine the state of the Native PHY and PLL IP cores.

You can enable the following optional reconfiguration logic options in the transceiver Native PHY and PLL IP cores:

  • Capability registers
  • Control and status registers
  • PRBS Soft Accumulators