L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 1/30/2024
Public
Document Table of Contents

7.2.4. Rate Switch Flag Register

The rate switch flag is for clock data recovery (CDR) charge pump calibration. Each SOF has CDR default charge pump settings. After power up, these settings are loaded into the PreSICE memory space. If you stream in a whole new memory initialization file (.MIF), the charge pump settings are stored into the Avalon® memory-mapped interface reconfiguration space. During RX PMA calibration (including CDR), PreSICE needs to know which set of CDR charge pump setting to use.

The default value of 0x100[3] is 0x0, PreSICE uses the settings in its memory space. If after a rate change you set 0x100[3]=0x1, PreSICE uses the setting from the Avalon® memory-mapped interface reconfiguration register. The rate switch flag only tells PreSICE where to obtain the CDR charge pump settings for CDR calibration. The rate switch flag should be used only when there is a rate change.

Multiple MIF files are required for rate change and reconfiguration. When the CDR charge pump setting registers 0x139[7] and 0x133[7:5] in the new MIF you want to stream in are different from the previous MIF, you must recalibrate with 0x100[3] = 0x1. If you stream in the whole MIF, the 0x100[3] is set to the correct value inside the MIF. If you stream in a reduced MIF, you must check whether or not CDR charge pump setting registers 0x139[7] and 0x133[7:5] are inside the reduced MIF. If the reduced MIF has these updated registers, you must set register 0x100[3]=0x1. If the reduced MIF does not include these updated registers, you need to set 0x100[3]=0x0.

Table 174.  Rate Switch Flag Register for CDR Calibration
Bit Description
0x100[3]

Rate switch flag register. Power up default value is 0x0.

0x0, PreSICE uses the default CDR charge pump bandwidth from the default memory space.

0x1, PreSICE uses the CDR charge pump bandwidth setting from the Avalon® memory-mapped interface space register space.