L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

8.2.1. Enabling Transceiver Toolkit Support

To enable transceiver toolkit support, you must enable the following parameters in the L-tile and H-tile Transceiver Native PHY IP and Transceiver PLL IP cores.

Table 175.  Parameters to Enable Transceiver Toolkit Support in L- and H-Tile Transceiver Native PHY IP Core
Parameter Description
Enable dynamic reconfiguration Allows you to change the configuration of the transceiver channels and PLLs without powering down the device.
Enable Native PHY Debug Master Endpoint (NPDME) Allows you to access the transceiver and PLL registers through System Console. When you recompile your design, the Intel Quartus Prime software inserts the NPDME debug fabric and embedded logic.
Share reconfiguration interface Enables you to use a single reconfiguration interface to control all channels. Enable this option when you use more than one channel.
Enable capability registers Enables capability registers that provide high-level information about the configuration of the transceiver channel.
Enable control and status registers Enables soft registers to read status signals and write control signals on the PHY interface through the embedded debug interface.
Enable prbs soft accumulators Enables soft logic for performing PRBS bit and error accumulation when you use the hard PRBS generator and checker.
Table 176.  Parameters to Enable Transceiver Toolkit Support in Transceiver PLL IP Cores
IP Core Parameter to Enable
Transceiver ATX PLL Intel FPGA IP
  • Enable dynamic reconfiguration
  • Enable Native PHY Debug Master Endpoint
CMU PLL Intel FPGA IP
fPLL Intel FPGA IP
The following figure illustrate the parameters that you must enable to debug transceivers in Intel® Stratix® 10 L-tile and H-tile transceiver designs.
Figure 256. Parameters to Enable Debugging in the L-Tile/H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP
The following figure illustrate the parameters that you must enable to debug an ATX PLL in Intel® Stratix® 10 L-tile and H-tile transceiver designs.
Figure 257. Parameters to Enable Debugging in the L-Tile/H-Tile Transceiver ATX PLL Intel® Stratix® 10 FPGA IP
You can either activate these settings when you first instantiate these components or modify the instances after preliminary compilation. Follow these steps for each transceiver IP core:
  1. In the IP Components tab of the Project Navigator, right click the IP instance, and click Edit in Parameter Editor.
  2. Turn on debug settings as shown in tables above.
    Note: Refer to the Dynamic Reconfiguration Parameters in Intel Stratix 10 GX Transceiver Native PHY IP Core and Dynamic Reconfiguration Parameters in Intel Stratix 10 GX Transceiver ATX PLL Core diagrams.
  3. Connect the reference signals that the debugging logic requires, if applicable. The NDPME requires connections for clock and reset signals. For details about frequency requirements, refer to the Ports and Parameters section.
  4. Click Generate HDL.
After enabling the parameters for all the IPs in the design and generating the HDL, recompile the project.

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