L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

A.4.6. Optional Reconfiguration Logic PHY- Control & Status

Enables users to read the status of channel and control the channels' behavior.
Name Address Type Attribute Name Encodings
RX Locked to Data Status

0x480[0]

read-only ch_rx_is_lockedtodata Shows the status of the current channel's rx_is_lockedtodata signal. 1'b1 indicates the receiver is locked to the incoming data.
RX Locked to Reference Status

0x480[1]

read-only ch_rx_is_lockedtoref Shows the status of the current channel's rx_is_lockedtoref signal. 1'b1 indicates the receiver is locked to the reference clock.
TX Calibration Busy Status

0x481[0]

read-only ch_tx_cal_busy Shows the status of the transmitter calibration status. 1'b1 indicates the transmitter calibration is in progress.
RX Calibration Busy Status

0x481[1]

read-only ch_rx_cal_busy Shows the status of the receiver calibration status. 1'b1 indicates the receiver calibration is in progress.
Avalon® memory-mapped interface Bus Busy Status

0x481[2]

read-only ch_avmm_busy

Shows the status of internal configuration bus arbitration.

When 1'b1, PreSICE has control of the internal configuration bus.

When 1'b0, you have control of the internal configuration bus. Refer to the Arbitration section for more details. Refer to the Calibration chapter for more details on calibration registers and performing user recalibration.

TX Calibration Busy Status Enable

0x481[4]

read-write ch_tx_cal_busy_enable

PMA channel tx_cal_busy output enable. The power up default value is 0x1.

1'b1: The tx_cal_busy output and ch_tx_cal_busy 0x481[0] are asserted high whenever PMA TX or RX calibration is running.

1'b0: The tx_cal_busy output or ch_tx_cal_busy 0x481[0] is never asserted high.

RX Calibration Busy Status Enable

0x481[5]

read-write ch_rx_cal_busy_enable

PMA channel rx_cal_busy output enable. The power up default value is 0x1.

1'b1: The rx_cal_busy output and ch_rx_cal_busy 0x481[1] are asserted high whenever PMA TX or RX calibration is running.

1'b0: The rx_cal_busy output or ch_rx_cal_busy 0x481[1] is never asserted high.

Set RX Lock to Data

0x4E0[0]

read-write ch_set_rx_locktodata Asserts the set_rx_locktodata signal to the receiver. See override_set_rx_locktodata row below. 1'b1 sets the NPDME set_rx_locktodata register.
Set RX Lock to Reference

0x4E0[1]

read-write ch_set_rx_locktoref Asserts the set_rx_locktoref signal to the receiver. See override_set_rx_locktoref row below. 1'b1 set the NPDME set_rx_locktoref register.
Override Set RX Lock to Data

0x4E0[2]

read-write ch_override_set_rx_locktodata

Selects whether the receiver listens to the NPDME set_rx_locktodata register or the rx_set_locktodata port.

1'b1 indicates the receiver listens to the NPDME set_rx_locktodata register.

1'b0 indicates the receiver listens to the NPDME set_rx_locktodata port.

Override Set RX Lock to Reference

0x4E0[3]

read-write ch_override_set_rx_locktoref

Selects whether the receiver listens to the NPDME set_rx_locktoref register or the rx_set_locktoref port.

1'b1 indicates the receiver listens to the NPDME set_rx_locktoref register.

1'b0 indicates the receiver listens to the NPDME set_rx_locktoref port.

RX Serial Loopback

0x4E1[0]

read-write ch_rx_seriallpbken Enables the rx_seriallpbken feature in the transceiver. 1'b1 enables serial loopback.

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