L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

1.1.3. Intel® Stratix® 10 MX H-Tile and E-Tile Configurations

The Intel® Stratix® 10 MX devices combine the programmability and flexibility of Intel® Stratix® 10 FPGAs and SoCs with 3D stacked high-bandwidth memory 2 (HBM2). The DRAM memory tile physically connects to the FPGA using Intel Embedded Multi-Die Interconnect Bridge (EMIB) technology.

Figure 10.  Intel® Stratix® 10 MX Device with 2 H-Tiles (48 Transceiver Channels) and 2 HBM2
Figure 11.  Intel® Stratix® 10 MX Device with 4 H-Tiles (96 Transceiver Channels) and Two 4 GB HBM2
Figure 12.  Intel® Stratix® 10 MX Device with 4 H-Tiles (96 Transceiver Channels) and Two 8 GB HBM2
Figure 13.  Intel® Stratix® 10 MX Device with 3 E-Tiles, 1 H-Tile (96 Transceiver Channels) and 2 HBM2

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