The deserialize x4 mode is used in high-speed applications where the FPGA fabric cannot operate as fast as the RX PCS.
In deserialize x4 mode, the byte deserializer deserializes 8-bit data into 32-bit data. As the parallel data width from the word aligner is quadrupled, the clock rate is divided four times.
Note: Depending on when the receiver PCS logic comes out of reset, the byte ordering at the output of the byte deserializer may or may not match the original byte ordering of the transmitted data. The byte misalignment resulting from byte deserialization is unpredictable because it depends on which byte is being received by the byte deserializer when it comes out of reset. Implement byte ordering logic in the FPGA fabric to retain the order of transmitted data.