A.2.1. CDR/CMU and PMA Calibration
|Internal configuration bus arbitration register||
This bit arbitrates the control of internal configuration bus
Write 1'b0 to control the internal configuration bus by user.
Write 1'b1 to pass the internal configuration bus control to PreSICE.
|PMA Calibration Status||
Status for calibration done or not done. This is an OR operation, and if both TX and RX calibration are enabled, PreSICE calibrates RX first, then TX. After both have completed, the calibration is complete.
This is inverted cal_busy signal.
1'b1: calibration done
1'b0: calibration not done
|PMA RX calibration enable||
PMA RX calibration enable
1'b1: RX calibration enable on
1'b0: RX calibration enable off
|PMA TX calibration enable||
PMA TX calibration enable
1'b1: TX calibration enable on
1'b0: TX calibration enable off
|Request PreSICE to configure the CDR/CMU PLL in preparation for reconfiguration||
Rate switch flag register when you use the PMA as a RX channel. The power up default value is 0x0.
0x0: PreSICE uses the default CDR charge pump bandwidth from the default memory space.
0x1: PreSICE uses the CDR charge pump bandwidth setting from the Avalon® memory-mapped interface space register space.
Request PreSICE to configure the PLL in preparation for reconfiguration when the PMA is configured as a CMU PLL:
1'b1: Request PreSICE to configure the PLL in reconfiguration mode
1'b0: Reconfiguration mode not requested
Request background calibration when the feature is enabled in the Native PHY IP core:
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