L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.5.1.6. fPLL IP Core Parameter Settings for PIPE

This section contains the recommended parameter values for this protocol. Refer to Using the Intel® Stratix® 10 L-Tile/H-Tile Transceiver Native PHY IP Core for the full range of parameter values.

Table 108.  fPLL Parameters for PCIe PIPE Gen1, Gen2, and Gen3 Modes
Parameter Gen1 PIPE Gen2 PIPE Gen3 PIPE
fPLL Mode Transceiver Transceiver Transceiver
Message level for rule violations Error Error Error
Protocol mode PCIe G1 PCIe G2 PCIe G2
Bandwidth Low, medium, high Low, medium, high Low, medium, high
Number of PLL reference clocks 1 1 1
Selected reference clock source 0 0 0
Enable fractional mode Off Off Off
VCCR_GXB and VCCT_GXB supply voltage for the transceiver 1_0V, 1_1V 1_0V, 1_1V 1_0V, 1_1V
Enable PCIe clock output port On On On
PLL output frequency 1250MHz 2500MHz 2500MHz
PLL output datarate 2500Mbps 5000Mbps 5000Mbps
PLL integer mode reference clock frequency 100MHz 100MHz 100MHz
Configure counters manually Off Off Off
Multiply factor (M-counter) N/A N/A N/A
Divide factor (N-counter) N/A N/A N/A
Divide factor (L-counter) N/A N/A N/A
Include Master clock generation block

x1 — Off

x2, x4, x8, x16 — On

x1 — Off

x2, x4, x8, x16 — On

Off
Clock division factor 1 1 N/A
Enable x24 non-bonded high – speed clock output port Off Off Off
Enable PCIe clock switch interface Off Off Off
Enable mcgb_rst and mcgb_rst_stat ports Off Off Off
Number of auxiliary MCGB clock input ports 0 0 0
MCGB input clock frequency 1250MHz 2500MHz 2500MHz
MCGB output data rate 2500Mbps 5000Mbps 5000Mbps
Enable bonding clock output ports

x1 — Off

x2, x4, x8, x16 — On

x1 — Off

x2, x4, x8, x16 — On

Off
PMA interface width 10 10 N/A
Table 109.  Master Clock Generation Block Options
Parameter Gen1 PIPE Gen2 PIPE Gen3 PIPE (For Gen1/Gen2 Speeds)
Include Master Clock Generation Block

x1: Off

x2, x4, x8, x16: On

x1: Off

x2, x4, x8, x16: On

x1, x2, x4, x8, x16: Off

Clock division factor

x1: N/A

x2, x4, x8, x16: 1

x1: N/A

x2, x4, x8, x16: 1

x1, x2, x4, x8, x16: N/A

Enable x6/xN non-bonded high-speed clock output port

x1: N/A

x2, x4, x8, x16: Off

x1: N/A

x2, x4, x8, x16: Off

x1, x2, x4, x8, x16: Off

Enable PCIe clock switch interface

x1: N/A

x2, x4, x8, x16: Off

x1: N/A

x2, x4, x8, x16: Off

x1, x2, x4, x8, x16: Off

Number of auxiliary MCGB clock input ports

x1: N/A

x2, x4, x8, x16: 0

x1: N/A

x2, x4, x8, x16: 0

x1, x2, x4, x8, x16: N/A

MCGB input clock frequency 1250 MHz 2500 MHz 2500 MHz
MCGB output data rate 2500 Mbps 5000 Mbps 5000 Mbps
Enable bonding clock output ports

x1: N/A

x2, x4, x8, x16: On

x1: N/A

x2, x4, x8, x16: On

x1, x2, x4, x8, x16: Off

PMA interface width

x1: N/A

x2, x4, x8, x16: 10

x1: N/A

x2, x4, x8, x16: 10

x1, x2, x4, x8, x16: N/A

Did you find the information on this page useful?

Characters remaining:

Feedback Message