L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

4.5. Using Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP

Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP is a configurable IP core that resets transceivers. You can use this IP core rather than creating your own user-coded reset controller. You can define a custom reset sequence for the IP core. You can also modify the IP cores's generated clear text Verilog HDL file to implement custom reset logic.

The Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP handles the reset sequence and supports the following options:

  • Separate or shared reset controls per channel
  • Separate controls for the TX and RX channels
  • Hysteresis for PLL locked status inputs
  • Configurable reset timing
  • Automatic or manual reset recovery mode in response to loss of PLL lock
  • Sequencing TX PCS Reset before RX PCS reset (for PIPE Application)

You should create your own reset controller if the Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP does not meet your requirements, especially when you require independent transceiver channel reset. The following figure illustrates the typical use of the Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP in a design that includes a transceiver PHY instance and the transmit PLL.

Figure 179. Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP System Diagram

The Transceiver PHY Reset Controller IP connects to the Transceiver PHY and the Transmit PLL. The Transceiver PHY Reset Controller IP receives status from the Transceiver PHY and the Transmit PLL. Based on the status signals or the reset input, it generates TX and RX reset signals to the Transceiver PHY.

The tx_ready signal indicates whether the TX PMA has exited the reset state, and if the TX PCS is ready to transmit data. The rx_ready signal indicates whether the RX PMA has exited the reset state, and if the RX PCS is ready to receive data. You must monitor these signals to determine when the transmitter and receiver are out of the reset sequence.

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