L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.2.5. Connect Datapath

Connect the transceiver PHY layer design to the Media Access Controller (MAC) IP core or to a data generator/analyzer or a frame generator/analyzer. Assign pins to all I/O's using the Assignment Editor or Pin Planner, or updating the Intel® Quartus® Prime Settings File (.qsf).
  1. Assign FPGA pins to all the transceiver and reference clock I/O pins. For more details, refer to the Intel® Stratix® 10 Device Family Pin Connection Guidelines.
  2. All of the pin assignments set using the Pin Planner and the Assignment Editor are saved in the <top_level_project_name>.qsf file. You can also directly modify the Intel® Quartus® Prime Settings File (.qsf).

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