L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 1/30/2024
Public
Document Table of Contents

2.5.1.4. How to Implement PCI Express (PIPE) in Intel® Stratix® 10 Transceivers

You must be familiar with the Standard PCS architecture, Gen3 PCS architecture, PLL architecture, and the reset controller before implementing the PCI Express protocol.

  1. Instantiate the Stratix 10 L-Tile/H-Tile Transceiver Native PHY IP from the IP Catalog (Installed IP > Library > Interface Protocols > Transceiver PHY > Stratix 10 L-Tile/H-Tile Transceiver Native PHY).
  2. Select Gen1/Gen2/Gen3 PIPE from the Stratix 10 Transceiver configuration rules list, located under Datapath Options.
  3. Use the parameter values in the tables in Native PHY IP Core Parameter Settings for PIPE as a starting point. Alternatively, you can use Stratix 10 L-Tile/H-Tile Transceiver Native PHY Presets . You can then modify the settings to meet your specific requirements.
  4. Click Finish to generate the Native PHY IP core (this is your RTL file).
  5. Instantiate and configure your PLL IP core.
  6. Create a transceiver reset controller. You can use your own reset controller or use the Transceiver PHY Reset Controller.
  7. Connect the Native PHY IP core to the PLL IP core and the Transceiver PHY Reset Controller. Use the information in Native PHY IP Core Ports for PIPE to connect the ports.
  8. Simulate your design to verify its functionality.
Figure 109.  Native PHY IP Core Connection Guidelines for a PIPE Gen3 Design