Visible to Intel only — GUID: oxk1484328110710
Ixiasoft
Visible to Intel only — GUID: oxk1484328110710
Ixiasoft
2.5.1.7. ATX PLL IP Core Parameter Settings for PIPE
This section contains the recommended parameter values for this protocol. Refer to Using the Intel® Stratix® 10 L-Tile/H-Tile Transceiver Native PHY IP Core for the full range of parameter values.
Parameter | Gen1 PIPE | Gen2 PIPE | Gen3 PIPE |
---|---|---|---|
Message level for rule violations | Error | Error | Error |
Protocol mode | PCIe Gen 1 | PCIe G2 | PCIe G3 |
Bandwidth | Low, medium, high | Low, medium, high | Low, medium, high |
Number of PLL reference clocks | 1 | 1 | 1 |
Selected reference clock source | 0 | 0 | 0 |
VCCR_GXB and VCCT_GXB supply voltage for the transceiver | 1_0V, 1_1V | 1_0V, 1_1V | 1_0V, 1_1V |
Primary PLL clock output buffer | GX clock output buffer | GX clock output buffer | GX clock output buffer |
Enable GX clock output port (tx_serial_clk) | On | On | On |
Enable GXT clock output port to above ATX PLL (gxt_output_to_abv_atx) | Off | Off | Off |
Enable GXT clock output port to below ATX PLL (gxt_output_to_blw_atx) | Off | Off | Off |
Enable GXT local clock output porttx_serial_clk_gxt) | Off | Off | Off |
Enable GXT clock input port from above ATX PLL (gxt_input_from_abv_atx) | Off | Off | Off |
Enable GXT clock input port from below ATX PLL (gxt_input_from_blw_atx) | Off | Off | Off |
Enable PCIe clock output port | On | On | Off 37 |
Enable ATX to fPLL cascade clock output port | N/A | N/A | N/A |
Enable GXT clock buffer to above ATX PLL | Off | Off | Off |
Enable GXT clock buffer to below ATX PLL | Off | Off | Off |
GXT output clock source | Disabled | Disabled | Disabled |
PLL output frequency | 1250MHz | 2500MHz | 4000MHz |
PLL output datarate | 2500Mbps | 5000Mbps | 8000Mbps |
PLL auto mode reference clock frequency(integer) | 100MHz | 100MHz | 100MHz |
Configure counters manually | Off | Off | Off |
Multiply factor (M-counter) | N/A | N/A | N/A |
Divide factor (N-counter) | N/A | N/A | N/A |
Divide factor (L-counter) | N/A | N/A | N/A |
Include Master clock generation block | x1 — Off x2, x4, x8, x16 — On |
x1 — Off x2, x4, x8, x16 — On |
x1 — Off x2, x4, x8, x16 — On |
Clock division factor | 1 | 1 | 1 |
Enable x24 non-bonded high – speed clock output port | Off | Off | Off |
Enable PCIe clock switch interface | Off | Off | On |
Enable mcgb_rst and mcgb_rst_stat ports | Off | Off | Off |
Number of auxiliary MCGB clock input ports | 0 | 0 | x1 — N/A x2, x4, x8, x16 — 1 |
MCGB input clock frequency | 1250MHz | 2500MHz | 4000MHz |
MCGB output data rate | 2500Mbps | 5000Mbps | 8000Mbps |
Enable bonding clock output ports | x1 — Off x2, x4, x8, x16 — On |
x1 — Off x2, x4, x8, x16 — On |
x1 — Off x2, x4, x8, x16 — On |
PMA interface width | 10 | 10 | 32 |
Enable Dynamic reconfiguration | On / Off | On / Off | On / Off |
Enable Native PHY debug master endpoint | On / Off | On / Off | On / Off |
Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE | Off | Off | Off |
Enable capability registers | On / Off | On / Off | On / Off |
Set user – defined IP identifier | <IP identifier> | <IP identifier> | <IP identifier> |
Enable control and status registers | On / Off | On / Off | On / Off |
Configuration file prefix | <File prefix> | <File prefix> | <File prefix> |
Generate SystemVerilog package file | On / Off | On / Off | On / Off |
Generate C header file | On / Off | On / Off | On / Off |
Generate MIF (Memory Initialization file) | On / Off | On / Off | On / Off |
Enable multiple reconfiguration profiles | Off | Off | Off |
Enable embedded reconfiguration streamer | Off | Off | Off |
Generate reduced reconfiguration files | Off | Off | Off |
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