L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

1.3.1. Transceiver Bank Architecture

Each L-Tile/H-tile transceiver tile contains four transceiver banks. The transceiver channels are grouped into transceiver banks, where each bank has six channels. These six channels are a combination of GX and GXT channels which you can configure in the following ways:

  • All six channels as GX channels
  • Channels 0, 1, 3, and 4 as GXT channels. L-Tile supports GXT channels in banks 1 and 3. H-Tile supports GXT channels in banks 0, 1, 2, and 3.
  • All six channels as a mix of GX and GXT channels; for example, two GX channels and four GXT channels on H-Tile Devices. On L-Tile devices, you can use a maximum of four channels in a bank when any channel is configured as a GXT channel.

Each channel can also run in any of the following operational modes:

  • Duplex (default)—Specifies a single channel that supports both transmission and reception
  • Transmitter (TX) Simplex—Specifies a single channel that supports only transmission
  • Receiver (RX) Simplex—Specifies a single channel that supports only reception

Each transceiver bank contains two Advanced Transmit (ATX) PLLs, two fractional PLLs (fPLL), and two Clock Multiplier Unit (CMU) PLLs.

Figure 15. Transceiver Banks in the L-Tile/H-Tile

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