L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

3.1.3.2. CMU PLL IP Core - Parameters, Settings, and Ports

Table 135.  CMU PLL IP Core - Parameters and Settings
Parameters Range Description

Number of PLL reference clocks

1 to 4

Specifies the number of input reference clocks for the CMU PLL.

You can use this parameter for data rate reconfiguration.

Selected reference clock source

0 to 3

Specifies the initially selected reference clock input to the CMU PLL.

Bandwidth

Low

Medium

High

PLL bandwidth specifies the ability of the PLL to track the input clock and jitter. PLL with "Low" bandwidth setting indicates better jitter rejection but a slower lock time. PLL with a "High" bandwidth has a faster lock time but tracks more jitter. A "Medium" bandwidth offers a balance between lock time and jitter rejection

VCCR_GXB and VCCT_GXB supply voltage for the Transceiver

1_0V, and 1_1V 47

Selects the VCCR_GXB and VCCT_GXB supply voltage for the Transceiver.

PLL reference clock frequency

Refer to the GUI

Selects the input reference clock frequency (MHz) for the PLL.

PLL output frequency

Refer to the GUI

Specify the target output frequency (MHz) for the PLL.

Table 136.  CMU PLL IP Core - Dynamic Reconfiguration
Parameters Range Description

Enable dynamic reconfiguration

On/Off

Enables the dynamic reconfiguration interface.

Enable Native PHY Debug Master Endpoint

On/Off

When enabled, the PLL IP includes an embedded Native PHY Debug Master Endpoint that connects internally Avalon® memory-mapped interface slave. The NPDME can access the reconfiguration space of the transceiver. It can perform certain test and debug functions via JTAG using the System Console. This option requires you to enable the "Share reconfiguration interface" option for configurations using more than 1 channel and may also require that a jtag_debug link be included in the system.

Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE

On/Off

When enabled, the reconfig_waitrequest does not indicate the status of Avalon® memory-mapped interface arbitration with PreSICE. The Avalon® memory-mapped interface arbitration status is reflected in a soft status register bit. This feature requires that the "Enable control and status registers" feature under "Optional Reconfiguration Logic" be enabled.

Enable capability registers

On/Off

Enables capability registers, which provide high level information about the transceiver PLL's configuration

Set user-defined IP identifier

0 to 255

Sets a user-defined numeric identifier that can be read from the user_identifer offset when the capability registers are enabled

Enable control and status registers

On/Off

Enables soft registers for reading status signals and writing control signals on the phy interface through the embedded debug. Available signals include pll_cal_busy, pll_locked and pll_powerdown.

Configuration file prefix

altera_xcvr_cdr_pll_s10

Specifies the file prefix to use for generated configuration files when enabled. Each variant of the IP should use a unique prefix for configuration files.

Generate SystemVerilog package file

On/Off

When enabled, The IP generates a SystemVerilog package file named "(Configuration file prefix)_reconfig_parameters.sv" containing parameters defined with the attribute values needed for reconfiguration.

Generate C header file

On/Off

When enabled, The IP generates a C header file named "(Configuration file prefix)_reconfig_parameters.h" containing macros defined with the attribute values needed for reconfiguration.

Generate MIF (Memory Initialize File)

On/Off

When enabled The IP generates an MIF (Memory Initialization File) named "(Configuration file prefix)_reconfig_parameters.mif". The MIF file contains the attribute values needed for reconfiguration in a data format.

Table 137.  CMU PLL IP Core - Parameter Summary
Parameters Range Description

Multiply factor (M-Counter)

1 to 5

Specifies the value for the feedback multiplier counter (M counter)

Divide factor (N-Counter)

0 to 4

Specifies the value for the pre-divider counter (N counter)

Divide factor (L-Counter)

Low

Medium

High

Specifies the value for the phase-frequency detector (PFD) circuit

Table 138.  CMU PLL IP Core - Ports
Port Range Clock Domain Description

pll_refclk0

input

N/A

Reference clock input port 0.

There are 5 reference clock input ports. The number of reference clock ports available depends on the Number of PLL reference clocks parameter.

pll_refclk1

input

N/A

Reference clock input port 1.

pll_refclk2

input

N/A

Reference clock input port 2.

pll_refclk3

input

N/A

Reference clock input port 3.

tx_serial_clk

output

N/A

High speed serial clock output port for GX channels. Represents the x1 clock network.

pll_locked

output

Asynchronous

Active high status signal which indicates if PLL is locked.

pll_cal_busy

output

Asynchronous

Status signal that is asserted high when PLL calibration is in progress.

Perform logical OR with this signal and the tx_cal_busy port on the reset controller IP.

47 Refer to the Intel® Stratix® 10 Device Datasheet for details about the minimum, typical, and maximum supply voltage specifications.

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