Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
High-Speed I/O Specifications DPA Lock Time Specifications LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications Memory Standards Supported by the Hard Memory Controller Memory Standards Supported by the Soft Memory Controller Memory Standards Supported by the HPS Hard Memory Controller DLL Range Specifications Memory Output Clock Jitter Specifications Performance Specifications of the HBM2 Interface in Intel® Stratix® 10 MX, NX, and DX 2100 Devices HBM2 Interface Performance OCT Calibration Block Specifications
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Intel® Stratix® 10 Device Datasheet
This datasheet describes the electrical characteristics, switching characteristics, configuration specifications, and timing for Intel® Stratix® 10 devices.
|Device Grade||Speed Grade Supported|
The suffix after the speed grade denotes the power options offered in Intel® Stratix® 10 devices.
- V—SmartVID with standard static power. For “V” suffix devices, both VCC and VCCP must share the same SmartVID regulator. VCCL_HPS can share the same SmartVID regulator or can use a separate fixed voltage regulator.
- L—0.85 V fixed voltage with low static power
- X—0.85 V fixed voltage with lowest static power
|Intel® Stratix® 10 GX||Final (Preliminary for 1SG040HF35 device only)|
|Intel® Stratix® 10 SX||Final (Preliminary for 1SX040HF35 device only)|
|Intel® Stratix® 10 TX||Final|
|Intel® Stratix® 10 MX||Final|
|Intel® Stratix® 10 DX||Final 1|
Note: The H-Tile Transmitter Specifications table is still preliminary.
1 Specifications related to Intel Intellectual Property (IP) products, UPI IP, and DDR-T IP are preliminary.
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