Intel® Stratix® 10 Device Datasheet

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ID 683181
Date 12/08/2023
Public
Document Table of Contents
Document Table of Contents x
Intel® Stratix® 10 Device Datasheet
Intel® Stratix® 10 Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Intel® Stratix® 10 Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up Resistor
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications x
Differential POD12 Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications L-Tile Transceiver Performance Specifications H-Tile Transceiver Performance Specifications E-Tile Transceiver Performance Specifications P-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications PLL Specifications DSP Block Specifications Memory Block Specifications Direct Interface Bus (DIB) Specifications Internal Temperature Sensing Diode Specifications External Temperature Sensing Diode Specifications Internal Voltage Sensor Specifications
PLL Specifications x
Fractional PLL Specifications I/O PLL Specifications
Periphery Performance Specifications x
High-Speed I/O Specifications DPA Lock Time Specifications LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications Memory Standards Supported by the Hard Memory Controller Memory Standards Supported by the Soft Memory Controller Memory Standards Supported by the HPS Hard Memory Controller DLL Range Specifications Memory Output Clock Jitter Specifications Performance Specifications of the HBM2 Interface in Intel® Stratix® 10 MX, NX, and DX 2100 Devices HBM2 Interface Performance OCT Calibration Block Specifications
L-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 L-Tile Devices Transceiver Specifications for Intel® Stratix® 10 L-Tile Devices
H-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 H-Tile Devices Transceiver Specifications for Intel® Stratix® 10 H-Tile Devices
E-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 E-Tile Devices Transceiver Reference Clock Specifications Transmitter Specifications for Intel® Stratix® 10 E-Tile Devices Receiver Specifications for Intel® Stratix® 10 E-Tile Devices
P-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 DX P-Tile Devices Transceiver Reference Clock Specifications Transmitter Specification for Intel® Stratix® 10 DX P-Tile Devices Receiver Specifications for Intel® Stratix® 10 DX P-Tile Devices
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
HPS PLL Specifications x
HPS PLL Input Requirements HPS PLL Performance
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® -ST Configuration Timing Configuration Bit Stream Sizes
Intel® Stratix® 10 Device Datasheet

High-Speed I/O Specifications

Table 37.  High-Speed I/O Specifications for Intel® Stratix® 10 Devices

When serializer/deserializer (SERDES) factor J = 3 to 10, use the SERDES block.

For LVDS applications, you must use the PLLs in integer PLL mode.

You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.

Symbol Condition –E1V, –I1V –E2V, –E2L, –I2L, –I2V, –C2L –E3V, –E3X, –I3X, –I3V Unit
Min Typ Max Min Typ Max Min Typ Max
fHSCLK_in (input clock frequency) True Differential I/O Standards Clock boost factor 
W = 1 to 40 58 10 — 800 10 — 700 10 — 625 MHz
fHSCLK_in (input clock frequency) Single-Ended I/O Standards Clock boost factor 
W = 1 to 40 58 10 — 625 10 — 625 10 — 525 MHz
fHSCLK_OUT (output clock frequency) — — — 800 59 — — 700 59 — — 625 59 MHz
Transmitter True Differential I/O Standards - fHSDR (data rate) 60 SERDES factor J = 4 to 10 61 63 62 63 — 1,600 63 — 1,434 64 63 — 1,250 Mbps
SERDES factor J = 3 61 63 62 63 — 1,000 63 — 1,000 63 — 938 Mbps
SERDES factor J = 2, uses DDR registers 63 — 840 65 63 — 65 63 — 65 Mbps
SERDES factor J = 1, uses DDR registers 63 — 420 65 63 — 65 63 — 65 Mbps
tx Jitter - True Differential I/O Standards Total jitter for data rate, 600 Mbps – 1.6 Gbps — — 160 — — 200 — — 250 ps
Total jitter for data rate, < 600 Mbps — — 0.1 — — 0.12 — — 0.15 UI
tDUTY 66 TX output clock duty cycle for Differential I/O Standards 45 50 55 45 50 55 45 50 55 %
tRISE & tFALL 62 67 True Differential I/O Standards — — 160 — — 180 — — 200 ps
TCCS 66 60 True Differential I/O Standards — — 330 — — 330 — — 330 ps
Receiver True Differential I/O Standards - fHSDRDPA (data rate) SERDES factor J = 4 to 10 61 63 62 150 — 1,600 150 — 1,43464 150 — 1,250 Mbps
SERDES factor J = 3 61 63 62 150 — 1,000 150 — 1,000 150 — 938 Mbps
fHSDR (data rate) (without DPA) 60 SERDES factor J = 3 to 10 63 — 68 63 — 68 63 — 68 Mbps
SERDES factor J = 2, uses DDR registers 63 — 65 63 — 65 63 — 65 Mbps
SERDES factor J = 1, uses DDR registers 63 — 65 63 — 65 63 — 65 Mbps
DPA (FIFO mode) DPA run length — — — 10,000 — — 10,000 — — 10,000 UI
DPA (soft CDR mode) DPA run length SGMII/GbE protocol — — 5 — — 5 — — 5 UI
All other protocols — — 50 data transition per 208 UI — — 50 data transition per 208 UI — — 50 data transition per 208 UI —
Soft CDR mode Soft-CDR ppm tolerance — –300 — 300 –300 — 300 –300 — 300 ppm
Non DPA mode Sampling Window — — — 330 — — 330 — — 330 ps
58 Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate.
59 This is achieved by using the PHY clock network.
60 Requires package skew compensation with PCB trace length.
61 The Fmax specification is based on the fast clock used for serial data. The interface Fmax is also dependent on the parallel clock domain which is design dependent and requires timing analysis.
62 The VCC and VCCP must be on a combined power layer and a maximum load of 5 pF for chip-to-chip interface.
63 The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or local) that you use. The I/O differential buffer and serializer do not have a minimum toggle rate.
64 Intel® Stratix® 10 GX 10M device only supports a maximum data rate of 1.4 Gbps.
65 The maximum ideal data rate is the SERDES factor (J) x the PLL maximum output frequency (fOUT) provided you can close the design timing and the signal integrity meets the interface requirements.
66 Not applicable for DIVCLK = 1.
67 This applies to default pre-emphasis and VOD settings only.
68 You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.
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