Intel® Stratix® 10 Device Datasheet

ID 683181
Date 12/08/2023
Document Table of Contents

HPS PLL Input Requirements

Table 81.  HPS PLL Input Requirements for Intel® Stratix® 10 DevicesThe main HPS PLL receives its clock signals from the HPS_OSC_CLK pin. Refer to the Intel Stratix 10 Device Family Pin Connection Guidelines for information about assigning this pin.
Description Min Typ Max Unit
Clock input range 25 125 MHz
Clock input accuracy 50 PPM
Clock input duty cycle 45 50 55 %