Intel® Stratix® 10 Device Datasheet

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ID 683181
Date 1/12/2022
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Transceiver Reference Clock Specifications

Table 75.  P-Tile Reference Clock Specifications For specification status, see the Data Sheet Status table
Symbol/Description Condition Min Typ Max Unit
Supported I/O standards HCSL
Input reference clock frequency 130 99.97 100 100.03 MHz
Rising edge rate 131 PCIe* 0.6 4 V/ns
Falling edge rate131 PCIe* 0.6 4 V/ns
Duty cycle PCIe* 40 60 %
Spread-spectrum modulating clock frequency 30 33 kHz
Spread-spectrum downspread –0.5 0 %
Absolute VMAX 1.15 V
Absolute VMIN –0.3 V
Peak-to-peak differential input voltage 300 1,500 mV
VICM (DC coupled) HCSL I/O standard for PCIe* reference clock 250 550 mV
Cycle to cycle jitter (TCCJITTER) 132 PCIe* 150 ps
TSSC-MAX-PERIOD-SLEW Max SSC df/dt 1,250 ppm/us
130 This number is with spread spectrum clocking (SSC) turned off. For systems with spread spectrum clocking, follow the specifications in Section 8.6.3 Data Rate Independent Refclk Parameters in the PCI Express Base Specification Revision 4.0.
131 Measured from -150 mV to +150 mV on the differential waveform. The 300 mV measurement window is centered on the differential zero crossing.
132 For common reference clock architecture, follow the jitter limit specified in the PCI Express* Card Electromechanical Specification for 2.5 GT/s, Section 4.3.7 Refclk Specifications for 5.0 GT/s and Section 4.3.8 Refclk Specifications for 8.0 GT/s in the PCI Express* Base Specification Revision 3.0, and the Section 8.6 Refclk Specifications for 16.0 GT/s in the PCI Express* Base Specification Revision 4.0.

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