Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
High-Speed I/O Specifications DPA Lock Time Specifications LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications Memory Standards Supported by the Hard Memory Controller Memory Standards Supported by the Soft Memory Controller Memory Standards Supported by the HPS Hard Memory Controller DLL Range Specifications Memory Output Clock Jitter Specifications Performance Specifications of the HBM2 Interface in Intel® Stratix® 10 MX, NX, and DX 2100 Devices HBM2 Interface Performance OCT Calibration Block Specifications
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Receiver Specifications for Intel® Stratix® 10 DX P-Tile Devices
|Supported I/O Standards||—||High Speed Differential I/O||—|
|Peak-to-peak differential input voltage VID (diff p-p)||PCIe* 2.5 GT/s 134||0.175||—||1.2||V|
|PCIe* 5.0 GT/s 134||0.1||—||1.2||V|
|PCIe* 8.0 GT/s||25 135||—||— 136||mV|
|PCIe* 16.0 GT/s||15 135||—||— 136||mV|
|Differential on-chip termination resistors||—||80||—||120||Ω|
134 Voltage shown for PCIe* 2.5 GT/s and 5.0 GT/s are at the package pins (TP2).
135 For PCIe* at 2.5 and 5 GT/s, the VID is measured at TP2, which is the accessible test point at the device under test. For PCIe* 8.0 GT/s and 16.0 GT/s, the VID is measured at TP2P. TP2P defines a reference point that comprehends the effects of the behavioral Rx package plus Rx equalization and represents the only location where a meaningful eye height and eye width limits can be defined.
136 The maximum eye height value depends on the transmitter launch voltage maximum value. Refer to the PCIe* Express Base Specification Rev. 4.0 for the generator (TX) launch voltage value.
137 Connecting RESREF at 169 Ω calibrates PCIe* channel on-chip termination to 85 Ω.
Did you find the information on this page useful?