Intel® Stratix® 10 Device Datasheet

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ID 683181
Date 12/08/2023
Public
Document Table of Contents
Document Table of Contents x
Intel® Stratix® 10 Device Datasheet
Intel® Stratix® 10 Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Intel® Stratix® 10 Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up Resistor
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications x
Differential POD12 Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications L-Tile Transceiver Performance Specifications H-Tile Transceiver Performance Specifications E-Tile Transceiver Performance Specifications P-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications PLL Specifications DSP Block Specifications Memory Block Specifications Direct Interface Bus (DIB) Specifications Internal Temperature Sensing Diode Specifications External Temperature Sensing Diode Specifications Internal Voltage Sensor Specifications
PLL Specifications x
Fractional PLL Specifications I/O PLL Specifications
Periphery Performance Specifications x
High-Speed I/O Specifications DPA Lock Time Specifications LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications Memory Standards Supported by the Hard Memory Controller Memory Standards Supported by the Soft Memory Controller Memory Standards Supported by the HPS Hard Memory Controller DLL Range Specifications Memory Output Clock Jitter Specifications Performance Specifications of the HBM2 Interface in Intel® Stratix® 10 MX, NX, and DX 2100 Devices HBM2 Interface Performance OCT Calibration Block Specifications
L-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 L-Tile Devices Transceiver Specifications for Intel® Stratix® 10 L-Tile Devices
H-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 H-Tile Devices Transceiver Specifications for Intel® Stratix® 10 H-Tile Devices
E-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 E-Tile Devices Transceiver Reference Clock Specifications Transmitter Specifications for Intel® Stratix® 10 E-Tile Devices Receiver Specifications for Intel® Stratix® 10 E-Tile Devices
P-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 DX P-Tile Devices Transceiver Reference Clock Specifications Transmitter Specification for Intel® Stratix® 10 DX P-Tile Devices Receiver Specifications for Intel® Stratix® 10 DX P-Tile Devices
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
HPS PLL Specifications x
HPS PLL Input Requirements HPS PLL Performance
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® -ST Configuration Timing Configuration Bit Stream Sizes
Intel® Stratix® 10 Device Datasheet

Receiver Specifications for Intel® Stratix® 10 DX P-Tile Devices

Table 78.  P-Tile Receiver Specifications For specification status, see the Data Sheet Status table
Symbol/Description Condition Min Typ Max Unit
Supported I/O Standards — High Speed Differential I/O —
Peak-to-peak differential input voltage VID (diff p-p) PCIe* 2.5 GT/s 131 0.175 — 1.2 V
PCIe* 5.0 GT/s 131 0.1 — 1.2 V
PCIe* 8.0 GT/s 25 132 — — 133 mV
PCIe* 16.0 GT/s 15 132 — — 133 mV
Differential on-chip termination resistors — 80 — 120 Ω
RESREF 134 — 167.3 169 170.7 Ω
RREF — 2.772 2.8 2.828 kΩ
131 Voltage shown for PCIe* 2.5 GT/s and 5.0 GT/s are at the package pins (TP2).
132 For PCIe* at 2.5 and 5 GT/s, the VID is measured at TP2, which is the accessible test point at the device under test. For PCIe* 8.0 GT/s and 16.0 GT/s, the VID is measured at TP2P. TP2P defines a reference point that comprehends the effects of the behavioral Rx package plus Rx equalization and represents the only location where a meaningful eye height and eye width limits can be defined.
133 The maximum eye height value depends on the transmitter launch voltage maximum value. Refer to the PCIe* Express Base Specification Rev. 4.0 for the generator (TX) launch voltage value.
134 Connecting RESREF at 169 Ω calibrates PCIe* channel on-chip termination to 85 Ω.
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