Intel® Stratix® 10 Device Datasheet

ID 683181
Date 1/12/2022
Document Table of Contents

Receiver Specifications for Intel® Stratix® 10 DX P-Tile Devices

Table 77.  P-Tile Receiver Specifications For specification status, see the Data Sheet Status table
Symbol/Description Condition Min Typ Max Unit
Supported I/O Standards High Speed Differential I/O
Peak-to-peak differential input voltage VID (diff p-p) PCIe* 2.5 GT/s 134 0.175 1.2 V
PCIe* 5.0 GT/s 134 0.1 1.2 V
PCIe* 8.0 GT/s 25 135 136 mV
PCIe* 16.0 GT/s 15 135 136 mV
Differential on-chip termination resistors 80 120
RESREF 137 167.3 169 170.7
RREF 2.772 2.8 2.828 kΩ
134 Voltage shown for PCIe* 2.5 GT/s and 5.0 GT/s are at the package pins (TP2).
135 For PCIe* at 2.5 and 5 GT/s, the VID is measured at TP2, which is the accessible test point at the device under test. For PCIe* 8.0 GT/s and 16.0 GT/s, the VID is measured at TP2P. TP2P defines a reference point that comprehends the effects of the behavioral Rx package plus Rx equalization and represents the only location where a meaningful eye height and eye width limits can be defined.
136 The maximum eye height value depends on the transmitter launch voltage maximum value. Refer to the PCIe* Express Base Specification Rev. 4.0 for the generator (TX) launch voltage value.
137 Connecting RESREF at 169 Ω calibrates PCIe* channel on-chip termination to 85 Ω.

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