Intel® Stratix® 10 Device Datasheet

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ID 683181
Date 1/12/2022
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HPS SPI Timing Characteristics

Table 83.  SPI Master Timing Requirements for Intel® Stratix® 10 DevicesYou can adjust the input delay timing by programming the rx_sample_dly register.
Symbol Description Min Typ Max Unit
Tspi_ref_clk The period of the SPI internal reference clock, sourced from l4_main_clk 2.5 ns
Tclk SPIM_CLK clock period 16.67 ns
Tdutycycle SPIM_CLK duty cycle 45 50 55 %
Tck_jitter SPIM_CLK output jitter 2 %
Tdio Master-out slave-in (MOSI) output skew –3 2 ns
Tdssfrst 143 SPI_SS_N asserted to first SPIM_CLK edge (1.5 × Tclk) – 2 ns
Tdsslst 143 Last SPIM_CLK edge to SPI_SS_N deasserted Tclk – 2 ns
Tsu 144 SPIM_MISO setup time with respect to SPIM_CLK capture edge 4.5 – (rx_sample_dly × T spi_ref_clk) 145 ns
Th 144 Input hold in respect to SPIM_CLK capture edge 1.3 + (rx_sample_dly× Tspi_ref_clk) ns
Figure 7. SPI Master Output Timing Diagram
Figure 8. SPI Master Input Timing Diagram
Table 84.  SPI Slave Timing Requirements for Intel® Stratix® 10 Devices
Symbol Description Min Typ Max Unit
Tspi_ref_clk The period of the SPI internal reference clock, sourced from l4_main_clk 2.5 ns
Tclk SPIM_CLK clock period 30 ns
Tdutycycle SPIM_CLK duty cycle 45 50 55 %
Td Master-in slave-out (MISO) output skew (2 × Tspi_ref_clk) + 3 (3 × Tspi_ref_clk) + 11 ns
Tsu Master-out slave-in (MOSI) setup time 4 ns
Th Master-out slave-in (MOSI) hold time 9 ns
Tsuss SPI_SS_N asserted to first SPIM_CLK edge Tspi_ref_clk + 4 ns
Thss Last SPIM_CLK edge to SPI_SS_N deasserted Tspi_ref_clk + 4 ns
Figure 9. SPI Slave Output Timing Diagram
Figure 10. SPI Slave Input Timing Diagram
143 SPI_SS_N behavior differs depending on Motorola SPI, TI SSP or Microwire operational mode.
144 The capture edge differs depending on the operational mode. For Motorola SPI, the capture edge can be the rising or falling edge depending on the scpol register bit; for TI SSP, the capture edge is the falling edge; for Microwire, the capture edge is the rising edge.
145 Valid values of rx_sample_dly range from 1 to 64 (units are in T spi_ref_clk steps).

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