Intel® Stratix® 10 Device Datasheet

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ID 683181
Date 1/12/2022
Public
Document Table of Contents

HPS Ethernet Media Access Controller (EMAC) Timing Characteristics

Table 87.  Reduced Gigabit Media Independent Interface (RGMII) TX Timing Requirements for Intel® Stratix® 10 Devices
Symbol Description Min Typ Max Unit
Tclk (1000Base-T) TX_CLK clock period 8 ns
Tclk (100Base-T) TX_CLK clock period 40 ns
Tclk (10Base-T) TX_CLK clock period 400 ns
Tdutycycle (1000Base-T) TX_CLK duty cycle 45 50 55 %
Tdutycycle(10/100Base-T) TX_CLK duty cycle 40 50 60 %

Td 148

149

TXD/TX_CTL to TX_CLK output skew –0.5 0.5 ns
Figure 13. RGMII TX and RMII TX Timing Diagram
Table 88.  RGMII RX Timing Requirements for Intel® Stratix® 10 Devices
Symbol Description Min Typ Max Unit
Tclk (1000Base-T) RX_CLK clock period 8 ns
Tclk (100Base-T) RX_CLK clock period 40 ns
Tclk (10Base-T) RX_CLK clock period 400 ns
Tdutycycle(1000Base-T) RX_CLK duty cycle 45 50 55 %
Tdutycycle(10/100Base-T) RX_CLK duty cycle 40 50 60 %
Tsu RX_D/RX_CTL to RX_CLK setup time 1 ns
Th 150 RX_CLK to RX_D/RX_CTL hold time 1 ns
Figure 14. RGMII RX and RMII RX Timing Diagram
Table 89.  Reduced Media Independent Interface (RMII) Clock Timing Requirements for Intel® Stratix® 10 Devices
Symbol Description Min Typ Max Unit
Tclk REF_CLK clock period, sourced by HPS TX_CLK 20 ns
REF_CLK clock period, sourced by external clock source 20 ns
Tdutycycle_int Clock duty cycle, REF_CLK sourced by TX_CLK 35 50 65 %
Tdutycycle_ext Clock duty cycle, REF_CLK sourced by external clock source 35 50 65 %
Table 90.  RMII TX Timing Requirements for Intel® Stratix® 10 Devices
Symbol Description Min Typ Max Unit
Td TX_CLK to TXD/TX_CTL output data delay 2 10 ns
Table 91.  RMII RX Timing Requirements for Intel® Stratix® 10 Devices
Symbol Description Min Typ Max Unit
Tsu RX_D/RX_CTL setup time 2 ns
Th RX_D/RX_CTL hold time 1 ns
Table 92.  Management Data Input/Output (MDIO) Timing Requirements for Intel® Stratix® 10 Devices
Symbol Description Min Typ Max Unit
Tclk MDC clock period 400 ns
Td MDC to MDIO output data delay 10 300 ns
Tsu Setup time for MDIO data 10 ns
Th Hold time for MDIO data 0 ns
Figure 15. MDIO Timing Diagram
148 Rise and fall times depend on the I/O standard, drive strength, and loading. Intel recommends simulating your configuration.
149 If you connect a PHY that does not implement clock-to-data skew, you can delay TX_CLK by 1.5—2.0 ns with the HPS I/O programmable delay, to meet the PHY's 1-ns data-to-clock skew requirement.
150

If you connect a PHY that does not implement clock-to-data skew, you can meet the HPS EMAC’s 1 ns setup time by delaying RX_CLK by 1.5-2 ns, using the HPS I/O programmable delay.

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