Intel® Stratix® 10 Device Datasheet

Download
ID 683181
Date 1/12/2022
Public
Document Table of Contents

Fractional PLL Specifications

Table 28.  Fractional PLL Specifications for Intel® Stratix® 10 DevicesThese specifications are applicable when fPLL is used in core mode.
Symbol  Parameter Condition Min Typ Max Unit
fIN Input clock frequency 29 800 45 MHz
fINPFD Input clock frequency to the phase frequency detector (PFD) 29 700 MHz
fVCO PLL voltage-controlled oscillator (VCO) operating range for core applications 6 14.025 GHz
tEINDUTY Input clock duty cycle 40 60 %
fOUT Output frequency for internal clock 1 GHz
fDYCONFIGCLK Dynamic configuration clock for reconfig_clk 125 MHz
tLOCK Time required to lock from end-of-device configuration 1 ms
tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) 1 ms
fCLBW PLL closed-loop bandwidth 0.3 4 MHz
tINCCJ 46, 47 Input clock cycle-to-cycle jitter FREF ≥ 100 MHz 0.13 UI (p-p)
FREF < 100 MHz ±650 ps (p-p)
tOUTPJ 48 Period jitter for clock output FOUT ≥ 100 MHz 600 ps (p-p)
FOUT < 100 MHz 60 mUI (p-p)
tOUTCCJ 48 Cycle-to-cycle jitter for clock output FOUT ≥ 100 MHz 600 ps (p-p)
FOUT < 100 MHz 60 mUI (p-p)
dKBIT Bit number of Delta Sigma Modulator (DSM) 32 bit
45 This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard and is dependent on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
46 A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps.
47 FREF is fIN/N, specification applies when N = 1.
48 External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter Specifications for Intel® Stratix® 10 Devices table.

Did you find the information on this page useful?

Characters remaining:

Feedback Message