Intel® Stratix® 10 Device Datasheet

ID 683181
Date 12/08/2023
Document Table of Contents
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HPS Trace Timing Characteristics

Table 96.  Trace Timing Requirements for Intel® Stratix® 10 Devices

To increase the trace bandwidth, Intel® recommends routing the trace interface to the FPGA in the HPS Platform Designer (Standard) component. The FPGA trace interface offers a 64-bit single data rate path that can be converted to double data rate to minimize FPGA I/O usage.

Depending on the trace module that you connect to the HPS trace interface, you may need to include board termination to achieve the maximum sampling speed possible. Refer to your trace module datasheet for termination recommendations.

Most trace modules implement programmable clock and data skew, to improve trace data timing margins. Alternatively, you can change the clock-to-data timing relationship with the HPS programmable I/O delay.

Symbol Description Min Typ Max Unit
Tclk Trace clock period 6.667 ns
Tclk_jitter Trace clock output jitter 2 %
Tdutycycle Trace clock maximum duty cycle 45 50 55 %
Td Tclk to D0–D15 output data delay 0 1.8 ns
Figure 25. Trace Timing Diagram