Intel® Stratix® 10 Device Datasheet

ID 683181
Date 12/08/2023
Document Table of Contents

POR Specifications

Power-on reset (POR) delay is defined as the delay between the time when all the power supplies monitored by the POR circuitry reach the minimum recommended operating voltage to the time when the nSTATUS is released high and your device is ready to begin configuration.

Table 100.  POR Delay Specification for Intel® Stratix® 10 Devices
POR Delay Minimum Maximum Unit
AS (Normal mode), AVST ×8, AVST ×16, AVST ×32 12 20 ms
AS (Fast mode) 2 6.5 ms