Intel® Stratix® 10 Device Datasheet

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ID 683181
Date 1/12/2022
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Avalon® -ST Configuration Timing

Table 103.   Avalon® -ST Timing Parameters for ×8, ×16, and ×32 Configurations in Intel® Stratix® 10 Devices
Symbol Description Minimum Maximum Unit
tACLKH AVST_CLK high time 3.6 ns
tACLKL AVST_CLK low time 3.6 ns
tACLKP AVST_CLK period 8 ns
tADSU 171 AVST_DATA setup time before rising edge of AVST_CLK 5.5 ns
tADH 171 AVST_DATA hold time after rising edge of AVST_CLK 0 ns
tAVSU AVST_VALID setup time before rising edge of AVST_CLK 5.5 ns
tAVDH AVST_VALID hold time after rising edge of AVST_CLK 0 ns
Figure 29.  Avalon® -ST Configuration Timing Diagram
171 Data sampled by the FPGA (sink) at the next rising clock edge.

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