Intel® Stratix® 10 Device Datasheet

ID 683181
Date 1/12/2022
Document Table of Contents

Receiver Specifications for Intel® Stratix® 10 E-Tile Devices

Table 71.  E-Tile Receiver Specifications
Symbol/Description Condition Minimum Typical Maximum Unit
Supported I/O Standards LVPECL
Absolute VMAX for a receiver pin123 NRZ VCCH_GXE + 0.3 V
Maximum peak-to-peak differential input voltage VID (diff p-p) before/after device configuration123 1.2 V
VCM (AC coupled)122 123 NRZ GND VCCH_GXE V
PAM4 GND + 0.3 VCCH_GXE – 0.3 V
Receiver run length124 100125 symbols
DC input impedance 40 60 Ω
DC differential input impedance 80 100 120 Ω
Powered down DC input impedance Receiver pin impedance when the receiver termination is powered down 100k Ω
Differential termination From DC to 100 MHz 80 100 120 Ω
PPM tolerance Allowed frequency mismatch between REFCLK and RX data 750 ppm
122 These values use internal AC-coupling. External AC-coupling capacitors are required when the RX input common mode voltage is beyond the range mentioned in this table (for PAM4 or NRZ). When using external AC-coupling capacitors, the RX termination is set to VCCH_GXE. When using internal AC-coupling capacitors, set the RX termination floating. The external AC-coupling capacitor has a typical value of at least 100 nF.
123 To support Hot Swap with E-tile, ensure the following:
  • RX inputs have external AC coupling capacitors of at least 100 nF.
  • The absolute voltage applied to the RX+ and RX- pins should not exceed ±300 mV (for a total of 600 mV p-p) (single ended).
  • The total differential voltage (combination of RX+/RX-) should not exceed 1,200 mV.
  • The transceiver termination selection must be external AC coupling (during mission mode).
124 No additional transition density requirements apply.
125 The incoming data must be statistically DC-balanced.

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