Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
High-Speed I/O Specifications DPA Lock Time Specifications LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications Memory Standards Supported by the Hard Memory Controller Memory Standards Supported by the Soft Memory Controller Memory Standards Supported by the HPS Hard Memory Controller DLL Range Specifications Memory Output Clock Jitter Specifications Performance Specifications of the HBM2 Interface in Intel® Stratix® 10 MX, NX, and DX 2100 Devices HBM2 Interface Performance OCT Calibration Block Specifications
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Receiver Specifications for Intel® Stratix® 10 E-Tile Devices
|Supported I/O Standards||—||LVPECL||—|
|Absolute VMAX for a receiver pin123||NRZ||—||VCCH_GXE + 0.3||—||V|
|Maximum peak-to-peak differential input voltage VID (diff p-p) before/after device configuration123||—||1.2||V|
|VCM (AC coupled)122 123||NRZ||GND||—||VCCH_GXE||V|
|PAM4||GND + 0.3||—||VCCH_GXE – 0.3||V|
|Receiver run length124||—||—||—||100125||symbols|
|DC input impedance||—||40||—||60||Ω|
|DC differential input impedance||—||80||100||120||Ω|
|Powered down DC input impedance||Receiver pin impedance when the receiver termination is powered down||100k||—||—||Ω|
|Differential termination||From DC to 100 MHz||80||100||120||Ω|
|PPM tolerance||Allowed frequency mismatch between REFCLK and RX data||—||—||750||ppm|
122 These values use internal AC-coupling. External AC-coupling capacitors are required when the RX input common mode voltage is beyond the range mentioned in this table (for PAM4 or NRZ). When using external AC-coupling capacitors, the RX termination is set to VCCH_GXE. When using internal AC-coupling capacitors, set the RX termination floating. The external AC-coupling capacitor has a typical value of at least 100 nF.
123 To support Hot Swap with E-tile, ensure the following:
- RX inputs have external AC coupling capacitors of at least 100 nF.
- The absolute voltage applied to the RX+ and RX- pins should not exceed ±300 mV (for a total of 600 mV p-p) (single ended).
- The total differential voltage (combination of RX+/RX-) should not exceed 1,200 mV.
- The transceiver termination selection must be external AC coupling (during mission mode).
124 No additional transition density requirements apply.
125 The incoming data must be statistically DC-balanced.
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