Intel® Stratix® 10 Device Datasheet

ID 683181
Date 1/12/2022
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HPS I2C Timing Characteristics

Table 93.  HPS I2C Timing Requirements for Intel® Stratix® 10 Devices
Symbol Description Standard Mode Fast Mode Unit
Min Max Min Max
Tclk Serial clock (SCL) clock period 10 2.5 μs
Tclk_jitter I2C clock output jitter 2 2 %
THIGH 151 SCL high period 4 152 0.6 153 μs
TLOW 154 SCL low period 4.7 155 1.3 156 μs
TSU;DAT Setup time for serial data line (SDA) data to SCL 0.25 0.1 μs
THD;DAT 157 Hold time for SCL to SDA data 0 3.15 0 0.6 μs
TVD;DAT and TVD;ACK 158 SCL to SDA output data delay 3.45 159 0.9 160 μs
TSU;STA Setup time for a repeated start condition 4.7 0.6 μs
THD;STA Hold time for a repeated start condition 4 0.6 μs
TSU;STO Setup time for a stop condition 4 0.6 μs
TBUF SDA high pulse duration between STOP and START 4.7 1.3 μs
Tscl:r 161 SCL rise time 1000 20 300 ns
Tscl:f 161 SCL fall time 300 6.54 300 ns
Tsda:r 161 SDA rise time 1000 20 300 ns
Tsda:f 161 SDA fall time 300 6.54 300 ns
Figure 16. I2C Timing Diagram
151 You can adjust Thigh using the ic_ss_scl_hcnt or ic_fs_scl_hcnt register.
152 The recommended minimum setting for ic_ss_scl_hcnt is 440.
153 The recommended minimum setting for ic_fs_scl_hcnt is 71.
154 You can adjust Tlow using the ic_ss_scl_lcnt or ic_fs_scl_lcnt register.
155 The recommended minimum setting for ic_ss_scl_lcnt is 500.
156 The recommended minimum setting for ic_fs_scl_lcnt is 141.
157 THD;DAT is affected by the rise and fall time.
158 TVD;DAT and TVD;ACK are affected by the rise and fall time, as well as the SDA hold time (set by adjusting the ic_sda_hold register).
159 Use maximum SDA_HOLD = 240 to be within the specification.
160 Use maximum SDA_HOLD = 60 to be within the specification.
161 Rise and fall time parameters vary depending on external factors such as the characteristics of the IO driver, pull-up resistor value, and total capacitance on the transmission line.

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