Intel® Stratix® 10 Device Datasheet

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ID 683181
Date 1/12/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Stratix® 10 Device Datasheet
Intel® Stratix® 10 Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Intel® Stratix® 10 Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up Resistor
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications L-Tile Transceiver Performance Specifications H-Tile Transceiver Performance Specifications E-Tile Transceiver Performance Specifications P-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications PLL Specifications DSP Block Specifications Memory Block Specifications Direct Interface Bus (DIB) Specifications Internal Temperature Sensing Diode Specifications External Temperature Sensing Diode Specifications Internal Voltage Sensor Specifications
PLL Specifications x
Fractional PLL Specifications I/O PLL Specifications
Periphery Performance Specifications x
High-Speed I/O Specifications DPA Lock Time Specifications LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications Memory Standards Supported by the Hard Memory Controller Memory Standards Supported by the Soft Memory Controller Memory Standards Supported by the HPS Hard Memory Controller DLL Range Specifications Memory Output Clock Jitter Specifications Performance Specifications of the HBM2 Interface in Intel® Stratix® 10 MX, NX, and DX 2100 Devices HBM2 Interface Performance OCT Calibration Block Specifications
L-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 GX/SX L-Tile Devices Transceiver Specifications for Intel® Stratix® 10 GX/SX L-Tile Devices
H-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 GX/SX/MX/TX H-Tile Devices Transceiver Specifications for Intel® Stratix® 10 GX/SX H-Tile Devices
E-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 E-Tile Devices Transceiver Reference Clock Specifications Transmitter Specifications for Intel® Stratix® 10 E-Tile Devices Receiver Specifications for Intel® Stratix® 10 E-Tile Devices
P-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 DX P-Tile Devices Transceiver Reference Clock Specifications Transmitter Specification for Intel® Stratix® 10 DX P-Tile Devices Receiver Specifications for Intel® Stratix® 10 DX P-Tile Devices
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
HPS PLL Specifications x
HPS PLL Input Requirements HPS PLL Performance
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® -ST Configuration Timing Configuration Bit Stream Sizes
Intel® Stratix® 10 Device Datasheet

HPS I2C Timing Characteristics

Table 93.  HPS I2C Timing Requirements for Intel® Stratix® 10 Devices
Symbol Description Standard Mode Fast Mode Unit
Min Max Min Max
Tclk Serial clock (SCL) clock period 10 — 2.5 — μs
Tclk_jitter I2C clock output jitter — 2 — 2 %
THIGH 151 SCL high period 4 152 — 0.6 153 — μs
TLOW 154 SCL low period 4.7 155 — 1.3 156 — μs
TSU;DAT Setup time for serial data line (SDA) data to SCL 0.25 — 0.1 — μs
THD;DAT 157 Hold time for SCL to SDA data 0 3.15 0 0.6 μs
TVD;DAT and TVD;ACK 158 SCL to SDA output data delay — 3.45 159 — 0.9 160 μs
TSU;STA Setup time for a repeated start condition 4.7 — 0.6 — μs
THD;STA Hold time for a repeated start condition 4 — 0.6 — μs
TSU;STO Setup time for a stop condition 4 — 0.6 — μs
TBUF SDA high pulse duration between STOP and START 4.7 — 1.3 — μs
Tscl:r 161 SCL rise time — 1000 20 300 ns
Tscl:f 161 SCL fall time — 300 6.54 300 ns
Tsda:r 161 SDA rise time — 1000 20 300 ns
Tsda:f 161 SDA fall time — 300 6.54 300 ns
Figure 16. I2C Timing Diagram
Related Information
151 You can adjust Thigh using the ic_ss_scl_hcnt or ic_fs_scl_hcnt register.
152 The recommended minimum setting for ic_ss_scl_hcnt is 440.
153 The recommended minimum setting for ic_fs_scl_hcnt is 71.
154 You can adjust Tlow using the ic_ss_scl_lcnt or ic_fs_scl_lcnt register.
155 The recommended minimum setting for ic_ss_scl_lcnt is 500.
156 The recommended minimum setting for ic_fs_scl_lcnt is 141.
157 THD;DAT is affected by the rise and fall time.
158 TVD;DAT and TVD;ACK are affected by the rise and fall time, as well as the SDA hold time (set by adjusting the ic_sda_hold register).
159 Use maximum SDA_HOLD = 240 to be within the specification.
160 Use maximum SDA_HOLD = 60 to be within the specification.
161 Rise and fall time parameters vary depending on external factors such as the characteristics of the IO driver, pull-up resistor value, and total capacitance on the transmission line.
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