Intel® Stratix® 10 Device Datasheet

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ID 683181
Date 1/12/2022
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Transceiver Performance for Intel® Stratix® 10 GX/SX L-Tile Devices

Table 45.   Intel® Stratix® 10 GX/SX L-Tile Transmitter and Receiver Datarate Performance
Symbol/Description Transceiver Speed Grade
-1 -2 -3
Chip-to-chip N/A 26.6 Gbps

8 channels per tile 76

17.4 Gbps
Backplane N/A 12.5 Gbps 12.5 Gbps
Note: Refer to the Transceiver Power Supply Operating Conditions for VCCR_GXB and VCCT_GXB specifications when using bonded and non-bonded transceiver channels in Intel® Stratix® 10 L-Tile devices.
Table 46.  L-Tile ATX PLL Performance
Symbol/Description Condition Transceiver Speed Grade 2 Transceiver Speed Grade 3 Unit
Supported Output Frequency Maximum Frequency 13.3 8.7 GHz
Minimum Frequency 500 MHz
tLOCK 77 Maximum Frequency 1 ms
tARESET Required Reset Time 78 79 25 Avalon Clock Cycles
Note: TX jitter specifications for the SerialLite III protocol at 17.4 Gbps are as low as: TJ = 0.32 UI, RJ = 0.15 UI, DJ = 0.18 UI, and DCD = 0.05 UI.
Table 47.  L-Tile fPLL Performance
Symbol/Description Condition Mode All Transceiver Speed Grades Unit
Supported Output Frequency (VCO frequency based) Maximum datarate Transceiver - HDMI 12.5 Gbps
Transceiver - General 12.5
Transceiver - OTN, SDI Cascade 14.025
Minimum datarate Transceiver - HDMI 4.6 Gbps
Transceiver - General 6
Transceiver - OTN, SDI Cascade 7
tLOCK 77 Maximum Frequency   1 ms
tARESET Required Reset Time 78 79   25 Avalon Clock Cycles
Table 48.  L-Tile CMU PLL Performance
Symbol/Description Condition All Transceiver Speed Grades Unit
Supported Output Frequency (VCO frequency based) Maximum Frequency 5.15625 GHz
Minimum Frequency 2.3 GHz
tLOCK 77 Maximum Frequency 1 ms
tARESET Required Reset Time 78 79 25 Avalon Clock Cycles
76 Refer to AN-778: Intel® Stratix® 10 Transceiver Usage for more details on channel selection requirements.
77 This specification applies after the ATX PLL, fPLL, or CMU PLL has completed calibration.
78 You must use the Avalon-MM interface to hold the PLLs in reset for the specified cycles by writing to the ATX PLL, fPLL, or CMU PLL pll_powerdown register.
79 You must assert pll_powerdown for a minimum of 25 cycles are required if you are using a 250-MHz AVMM clock.

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