Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
High-Speed I/O Specifications DPA Lock Time Specifications LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications Memory Standards Supported by the Hard Memory Controller Memory Standards Supported by the Soft Memory Controller Memory Standards Supported by the HPS Hard Memory Controller DLL Range Specifications Memory Output Clock Jitter Specifications Performance Specifications of the HBM2 Interface in Intel® Stratix® 10 MX, NX, and DX 2100 Devices HBM2 Interface Performance OCT Calibration Block Specifications
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Recommended Operating Conditions
|Symbol||Description||Condition||Minimum 9||Typical||Maximum 9||Unit|
|VCC||Core voltage power supply for Intel® Stratix® 10 GX 10M device||–E2L, –C2L||0.85||0.88||0.91||V|
|Core voltage power supply for all other Intel® Stratix® 10 devices||–E1V, –I1V, –E2V, –I2V, –E3V, –I3V 10||(Typical) – 30 mV||0.8 – 0.94||(Typical) + 30 mV||V|
|–E2L, –I2L, –E3X, –I3X||0.82||0.85||0.88||V|
|VCCP||Periphery circuitry and transceiver fabric interface power supply for Intel® Stratix® 10 GX 10M device||–E2L, –C2L||0.85||0.88||0.91||V|
|Periphery circuitry and transceiver fabric interface power supply for all other Intel® Stratix® 10 devices||–E1V, –I1V, –E2V, –I2V, –E3V, –I3V 10||(Typical) – 30 mV||0.8 – 0.94||(Typical) + 30 mV||V|
|–E2L, –I2L, –E3X, –I3X||0.82||0.85||0.88||V|
|VCCIO_SDM||Configuration pins power supply||1.8 V||1.71||1.8||1.89||V|
|VCCPLLDIG_SDM||Secure Device Manager (SDM) block PLL digital power supply||—||0.87||0.9||0.93||V|
|VCCPLL_SDM||SDM block PLL analog power supply||—||1.71||1.8||1.89||V|
|VCCFUSEWR_SDM||Fuse block writing power supply||—||2.35||2.4||2.45||V|
|VCCADC||ADC voltage sensor power supply||—||1.71||1.8||1.89||V|
|VCCERAM||Embedded memory and digital transceiver power supply||0.9 V||0.87||0.9||0.93||V|
|VCCBAT 11||Battery back-up power supply (For design security volatile key register)||—||1.2||—||1.8||V|
|VCCPT||Power supply for programmable regulator and I/O pre-driver||1.8 V||1.71||1.8||1.89||V|
|VCCIO||I/O buffers power supply for LVDS I/O (except for 1SG040HF35 and 1SX040HF35 banks 3C and 3D)||1.8 V||1.71||1.8||1.89||V|
|VCCIO3V||I/O buffers power supply for 3 V I/O||3.0 V||2.85||3||3.15||V|
|VCCIO3C||I/O buffers power supply for 1SG040HF35 and 1SX040HF35 devices bank 3C only||3.3 V||3.135||3.3||3.465||V|
|VCCIO3D||I/O buffers power supply for 1SG040HF35 and 1SX040HF35 devices bank 3D only||1.8 V||1.71||1.8||1.89||V|
|VCCIO_UIB||Power supply for the Universal Interface Bus between the core and embedded HBM2 memory||1.2 V||1.17||1.2||1.23||V|
|VCCM_WORD||Power supply for the embedded HBM2 memory||—||2.4||2.5||2.6||V|
|VCCA_PLL||PLL analog voltage regulator power supply||—||1.71||1.8||1.89||V|
|VI 12 13||DC input voltage||3.3 V I/O||–0.3||—||VCCIO + 0.33||V|
|3 V I/O||–0.3||—||VCCIO + 0.65||V|
|LVDS I/O||–0.3||—||VCCIO + 0.3||V|
|TJ||Operating junction temperature for Intel® Stratix® 10 MX, NX, and DX 2100 devices||Extended 14||0||—||100 15||°C|
|Operating junction temperature for Intel® Stratix® 10 GX 10M device||Commercial||25||—||85||°C|
|Operating junction temperature for all other Intel® Stratix® 10 devices||Extended||0||—||100||°C|
|Industrial||–40 (–20 for E-tile devices) 16||—||100||°C|
|tRAMP 17 18 19||Power supply ramp time||Standard POR||200 μs||—||100 ms||—|
9 This value describes the required voltage measured between the PCB power and ground ball during normal device operation. The voltage ripple includes both regulator DC ripple and the dynamic noise. Refer to power distribution network (PDN) tool for PCB power distribution network design.
10 The use of Power Management Bus (PMBus*) voltage regulator dedicated to Intel® Stratix® 10 SmartVID devices is mandatory for VCC and VCCP. The PMBus* voltage regulator and Intel® Stratix® 10 SmartVID devices are connected via PMBus*.
11 Intel recommends connecting VCCBAT to a 1.8 V power supply if you do not use the design security feature in Intel® Stratix® 10 devices.
12 The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.
13 This value applies to both input and tri-stated output configuration. Pin voltage should not be externally pulled higher than the maximum value.
14 Intel® Stratix® 10 MX, NX, and DX 2100 devices are generally offered in Extended temperature range only. If Industrial temperature range is required, note that you can configure these devices at less than 0°C, but the HBM2 interface will be held in reset and will not be calibrated until TJ reaches 0°C. Contact your Intel sales representative for the availability of Intel® Stratix® 10 MX, NX, and DX 2100 Industrial temperature range devices.
15 Recommended maximum operating temperature for HBM2 is 95°C.
16 E-tile supports an operating temperature range of –40°C to 100°C. However, the E-tile transceivers may experience a higher error rate from –40°C to –20°C because of the calibration procedure when starting at a low temperature. Therefore, the recommended operating temperature range for E-tile protocol-compliant transceiver links is –20°C to 100°C. The environmental temperature ramp rate for the device is limited to 2°C per minute, otherwise, the device would not be compliant and may lead to link activity failure.
17 tRAMP is the ramp time of each individual power supply, not the ramp time of all combined power supplies.
18 To support AS fast mode, all power supplies to the Intel® Stratix® 10 device must be fully ramped-up within 10 ms to the recommended operating conditions.
19 To support AS normal mode, VCCIO_SDM of the Intel® Stratix® 10 device must be fully ramped-up within 10 ms to the recommended operating condition.
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