Intel® Stratix® 10 Device Datasheet

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ID 683181
Date 1/12/2022
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Transceiver Specifications for Intel® Stratix® 10 GX/SX H-Tile Devices

Table 60.  H-Tile Reference Clock Specifications
Symbol/Description Condition Min Typ Max Unit
Supported I/O Standards Dedicated reference clock pin CML, Differential LVPECL, LVDS, and HCSL
RX reference clock pin CML, Differential LVPECL, and LVDS

Input Reference Clock Frequency (CMU PLL)

  50 800 MHz

Input Reference Clock Frequency (ATX PLL)

  100 800 MHz

Input Reference Clock Frequency (fPLL PLL)

  25 99/50 800 MHz
Rise time 20% to 80% 350 ps
Fall time 80% to 20% 350 ps
Duty cycle 45 55 %
Spread-spectrum modulating clock frequency PCIe 30 33 kHz
Spread-spectrum downspread PCIe 0 to –0.5 %
On-chip termination resistors 100 Ω
Absolute VMAX Dedicated reference clock pin 1.6 V
RX reference clock pin 1.2 V
Absolute VMIN –0.4 V
Peak-to-peak differential input voltage 200 1600 mV
VICM (AC coupled) VCCR_GXB =1.03 V 0 V
VCCR_GXB = 1.12 V 0 V
VICM (DC coupled) HCSL I/O standard for PCIe reference clock 250 550 mV
Transmitter REFCLK Phase Noise (800 MHz) 100 101 100 Hz –70 dBc/Hz
1 kHz –90 dBc/Hz
10 kHz –100 dBc/Hz
100 kHz –110 dBc/Hz
≥ 1 MHz –120 dBc/Hz
RREF 2.0 k ±1% Ω
TSSC-MAX-PERIOD-SLEW Max SSC df/dt     0.75  
Note: When using PCI Express, you must meet the reference clock phase jitter requirements as specified in the 4.3.7 Refclk Specifications for 2.5 GT/s and 5.0 GT/s and 4.3.8 Refclk Specification for 8.0 GT/s sections of the PCI Express Base Specification Revision 3.0.
Table 61.  H-Tile Transceiver Clock Network Maximum Data Rate Specifications
Clock Network Maximum Performance 102 Channel Span Unit
ATX fPLL CMU
x1 17.4 12.5 10.3125 6 channels Gbps
x6 17.4 12.5 N/A 6 channels Gbps
x24 17.4 106 12.5 N/A

2 banks up and 1 bank down (total 24 channels)

or

2 banks down and 1 bank up (total 24 channels)

Gbps
GXT clock lines 28.3 N/A N/A 4 GXT channels within the same transceiver bank and 2 from the bank above or 2 from the bank below. 103 Gbps
Table 62.  H-Tile Receiver Specifications
Symbol/Description Condition All Transceiver Speed Grades Unit
Min Typ Max
Supported I/O Standards High Speed Differential I/O, CML, Differential LVPECL, and LVDS
Absolute VMAX for a receiver pin 104 1.2 V
Absolute VMIN for a receiver pin 105 -0.4 V
Maximum peak-to-peak differential input voltage VID (diff p-p) before device configuration 2.0 V
Maximum peak-to-peak differential input voltage VID (diff p-p) after device configuration VCCR_GXB = 1.03 V 2.0 V
VCCR_GXB = 1.12 V 106, 107 1.8 V
Differential on-chip termination resistors 85-Ω setting 85 ± 20% Ω
100-Ω setting 100 ± 20% Ω
VICM (AC coupled) VCCR_GXB = 1.03 V 107 700 mV
VCCR_GXB = 1.12 V 107 750 mV
tLTR 108 1 ms
tLTD 109 4 µs
tLTD_manual 110 4 µs
tLTR_LTD_manual 111 15 µs
Run Length 200 UI
CDR ppm tolerance PCIe-only -300 300 ppm
All other protocols -1000 1000 ppm
Table 63.  H-Tile Transmitter SpecificationsThe data in this table is preliminary.
Symbol/Description Condition Transceiver Speed Grade 3 Unit
Min Typ Max
Supported I/O Standards High Speed Differential I/O 112
Differential on-chip termination resistors 85-Ω setting 85 ± 20% Ω
100-Ω setting 100 ± 20% Ω
VOCM (AC coupled) VCCT_GXB = 1.03 V 113 515 mV
VOCM (AC coupled) VCCT_GXB = 1.12 V 113 560 mV
VOCM (DC coupled) 114 VCCT_GXB = 1.03 V 113 515 mV
VOCM (DC coupled) 114 VCCT_GXB = 1.12 V 113 560 mV
Rise time 115 20% to 80% 20 130 ps
Fall time 115 80% to 20% 20 130 ps
Intra-differential pair skew TX VCM = 0.5 V and slew rate of 15 ps 15 116 ps
Table 64.  H-Tile Typical Transmitter VOD Settings
Symbol VOD Setting 117 VOD/VCCT_GXB Ratio
VOD differential value = VOD/VCCT_GXB ratio x VCCT_GXB 31 1.00
30 0.97
29 0.93
28 0.90
27 0.87
26 0.83
25 0.80
24 0.77
23 0.73
22 0.70
21 0.67
20 0.63
19 0.60
18 0.57
17 0.53
16 0.50
15 0.47
14 0.43
13 0.40
12 0.37
Table 65.  H-Tile Transmitter Channel-to-channel Skew Specifications
Mode Channel Span Maximum Skew Unit
x6 Clock Up to 6 channels in one bank 61 ps
x24 Clock Up to 24 channels in one bank 500 118 ps
Table 66.  Transceiver Clocks Specifications for Intel® Stratix® 10 GX/SX H-Tile Devices
Clock Value Unit
reconfig_clk ≤ 150 MHz
fixed_clk for the RX detect circuit 250 ± 20% MHz

For OSC_CLK_1 specifications, refer to the External Configuration Clock Source Requirements section.

99 The 25 MHz is only available when HDMI is selected for fPLL protocol mode.
100 To calculate the REFCLK phase noise requirement at frequencies other than 800 MHz, use the following formula: REFCLK phase noise at f (MHz) = REFCLK phase noise at 800 MHz + 20*log(f/800).
101 A phase noise (PN) mask overrides the REFCLK noise.
102 The maximum data rate depends on speed grade.
103 If the upper ATX PLL in a bank is used as the main GXT PLL, then the channel span includes two GXT channels from the bank above. If the lower ATX PLL in a bank is used as the main GXT PLL, then the channel span includes two GXT channels from the bank below.
104 The device cannot tolerate prolonged operation at this absolute maximum.
105 A passive pull up resistance prevents a 0-V common mode voltage on AC coupled receiver pins before the FPGA is configured.
106 Bonded channels operating at data rates above 16 Gbps require 1.12 V ± 20 mV at the pin. For channels that are placed in the same H-Tile as the channels that required 1.12 V ± 20 mV, VCCR_GXB = 1.12 V ± 20 mV.
107 For GXT channels, VCCR_GXB must be 1.12 V. For GX channels, VCCR_GXB must be 1.03 V. VCCR_GXB must be 1.12 V for the transceiver on the same H-Tile when using GX and GXT channels together.
108 tLTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset or after CDR calibration is completed.
109 tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high.
110 tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is functioning in the manual mode.
111 tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when the CDR is functioning in the manual mode.
112 High Speed Differential I/O is the dedicated I/O standard for the transmitter in Intel® Stratix® 10 transceivers.
113 For GXT channels, VCCT_GXB must be 1.12 V. For GX channels, VCCT_GXB must be 1.03 V. VCCT_GXB must be 1.12 V when using GX and GXT channels together within the same H-Tile.
114 DC coupling specifications are pending silicon characterization.
115 The Intel® Quartus® Prime software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.
116 This specification pertains to Hyper Memory Cube.
117 Intel recommends a VOD ranging from 31 to 17.
118 500 ps is not supported for all configurations and depends upon the Master CGB placement.

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