Intel® Stratix® 10 Device Datasheet

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ID 683181
Date 1/12/2022
Public
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HPS PLL Performance

Table 81.  HPS PLL Performance for Intel® Stratix® 10 Devices
Description Min Max Unit
Main PLL VCO output 3000 MHz
Peripheral PLL VCO output 3000 MHz
h2f_user0_clk 141 500 MHz
h2f_user1_clk 141 500 MHz
141 The HPS PLL provides this clock to the FPGA fabric.

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