Intel® Stratix® 10 Device Datasheet

ID 683181
Date 12/08/2023
Document Table of Contents

HPS PLL Performance

Table 82.  HPS PLL Performance for Intel® Stratix® 10 Devices
Description Min Max Unit
Main PLL VCO output 3000 MHz
Peripheral PLL VCO output 3000 MHz
h2f_user0_clk 138 500 MHz
h2f_user1_clk 138 500 MHz
138 The HPS PLL provides this clock to the FPGA fabric.