Intel® Stratix® 10 Device Datasheet

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ID 683181
Date 1/12/2022
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Transceiver Specifications for Intel® Stratix® 10 GX/SX L-Tile Devices

Table 49.  L-Tile Reference Clock Specifications
Symbol/Description Condition All Transceiver Speed Grades Unit
Min Typ Max
Supported I/O Standards Dedicated reference clock pin CML, Differential LVPECL, LVDS, and HCSL
RX reference clock pin CML, Differential LVPECL, and LVDS

Input Reference Clock Frequency

(CMU PLL)

  50 800 MHz

Input Reference Clock Frequency

(ATX PLL)

  100 800 MHz

Input Reference Clock Frequency

(fPLL)

  50 80 800 MHz
Rise time 20% to 80% 350 ps
Fall time 80% to 20% 350 ps
Duty cycle 45 55 %
Spread-spectrum modulating clock frequency PCIe 30 33 kHz
Spread-spectrum downspread PCIe 0 to –0.5 %
On-chip termination resistors 100 Ω
Absolute VMAX Dedicated reference clock pin 1.6 V
RX reference clock pin 1.2 V
Absolute VMIN –0.4 V
Peak-to-peak differential input voltage 200 1600 mV
VICM (AC coupled) VCCR_GXB =1.03 V 0 V
VICM (DC coupled) HCSL I/O standard for PCIe reference clock 250 550 mV
Transmitter REFCLK Phase Noise (800 MHz) 81 100 Hz –70 dBc/Hz
1 kHz –90 dBc/Hz
10 kHz –100 dBc/Hz
100 kHz –110 dBc/Hz
≥ 1 MHz –120 dBc/Hz
RREF 2.0 k ±1% 2.0 k ±1% Ω
TSSC-MAX-PERIOD-SLEW Max spread spectrum clocking (SSC) df/dt     0.75  
Note: When using PCI Express, you must meet the reference clock phase jitter requirements as specified in the 4.3.7 Refclk Specifications for 2.5 GT/s and 5.0 GT/s and 4.3.8 Refclk Specification for 8.0 GT/s sections of the PCI Express Base Specification Revision 3.0.
Table 50.  L-Tile Transceiver Clock Network Maximum Data Rate Specifications
Clock Network Maximum Performance 82 Channel Span Unit
ATX fPLL CMU
x1 17.4 12.5 10.3125 6 channels Gbps
x6 17.4 12.5 N/A 6 channels Gbps
x24 17.4 86 12.5 N/A

2 banks up and 1 bank down (total 24 channels)

or

2 banks down and 1 bank up (total 24 channels)

Gbps
GXT clock lines 26.6 N/A N/A 4 GXT channels within the same transceiver bank and 2 from the bank above or 2 from the bank below. 83 Gbps
Table 51.  L-Tile Receiver Specifications
Symbol/Description Condition Transceiver Speed Grade 3 Unit
Min Typ Max
Supported I/O Standards High Speed Differential I/O, CML, Differential LVPECL, and LVDS
Absolute VMAX for a receiver pin 84 1.2 V
Absolute VMIN for a receiver pin 84 85 -0.4 V
Maximum peak-to-peak differential input voltage VID (diff p-p) before device configuration 2.0 V
Maximum peak-to-peak differential input voltage VID (diff p-p) after device configuration VCCR_GXB = 1.03 V 86 2.0 V
VCCR_GXB = 1.12 V 1.8 V
Differential on-chip termination resistors 85-Ω setting 85 ± 20% Ω
100-Ω setting 100 ± 20% Ω
VICM (AC coupled) VCCR_GXB = 1.03 V 700 mV
VCCR_GXB = 1.12 V 750 mV
tLTR 87 1 ms
tLTD 88 4 µs
tLTD_manual 89 4 µs
tLTR_LTD_manual 90 15 µs
Run Length 200 UI
CDR ppm tolerance PCIe-only -300 300 ppm
All other protocols -1000 1000 ppm
Table 52.  L-Tile Transmitter Specifications
Symbol/Description Condition Transceiver Speed Grade 2 and 3 Unit
Min Typ Max
Supported I/O Standards High Speed Differential I/O 91
Differential on-chip termination resistors 85-Ω setting 85 ± 20% Ω
100-Ω setting 100 ± 20% Ω
VOCM (AC coupled) VCCT_GXB = 1.03 V 515 mV
Rise time 92 20% to 80% 20 130 ps
Fall time 92 80% to 20% 20 130 ps
Intra-differential pair skew TX VCM = 0.5 V and slew rate of 15 ps 15 93 ps
Table 53.  L-Tile Typical Transmitter VOD Settings
Symbol VOD Setting 94 VOD/VCCT_GXB Ratio
VOD differential value = VOD/VCCT_GXB ratio x VCCT_GXB 31 1.00
30 0.97
29 0.93
28 0.90
27 0.87
26 0.83
25 0.80
24 0.77
23 0.73
22 0.70
21 0.67
20 0.63
19 0.60
18 0.57
17 0.53
16 0.50
15 0.47
14 0.43
13 0.40
12 0.37
Table 54.  L-Tile Transmitter Channel-to-channel Skew Specifications
Mode Channel Span Maximum Skew Unit
x6 Clock Up to 6 channels in one bank 61 ps
x24 Clock Up to 24 channels in one tile 500 95 ps
Table 55.  Transceiver Clocks Specifications for Intel® Stratix® 10 L-Tile Devices
Clock Value Unit
reconfig_clk ≤ 150 MHz
fixed_clk for the RX detect circuit 250 ± 20% MHz

For OSC_CLK_1 specifications, refer to the External Configuration Clock Source Requirements section.

80 The fMIN is 25 MHz when the fPLL is used for the HDMI protocol.
81 To calculate the REFCLK phase noise requirement at frequencies other than 800 MHz, use the following formula: REFCLK phase noise at f (MHz) = REFCLK phase noise at 800 MHz + 20*log(f/800).
82 The maximum data rate depends on speed grade.
83 If the upper ATX PLL in a bank is used as the main GXT PLL, then the channel span includes two GXT channels from the bank above. If the lower ATX PLL in a bank is used as the main GXT PLL, then the channel span includes two GXT channels from the bank below.
84 The device cannot tolerate prolonged operation at this absolute maximum.
85 A passive pull up resistance prevents a 0-V common mode voltage on AC coupled receiver pins before the FPGA is configured.
86 Bonded channels operating at data rates above 16 Gbps require 1.12 V ± 20 mV at the pin. For a given L-Tile, if there are channels that need the higher power supply, tie all the channels on that side to the higher power supply.
87 tLTR is the time required for the receiver CDR to lock to the input reference clock frequency after coming out of reset, or after the CDR's calibration is complete.
88 tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high.
89 tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is functioning in the manual mode.
90 tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when the CDR is functioning in the manual mode.
91 High Speed Differential I/O is the dedicated I/O standard for the transmitter in Intel® Stratix® 10 L-/H-Tile transceivers.
92 The Intel® Quartus® Prime software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.
93 This specification pertains to Hyper Memory Cube.
94 Intel recommends a VOD ranging from 31 to 17.
95 500 ps is not supported for all configurations and depends upon the Master CGB placement.

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