Intel® Stratix® 10 Device Datasheet

ID 683181
Date 1/12/2022
Document Table of Contents

Transmitter Specification for Intel® Stratix® 10 DX P-Tile Devices

Table 76.  P-Tile Transmitter Specifications For specification status, see the Data Sheet Status table. AC coupling capacitors required for PCIe* links are placed on the board external to the Intel® Stratix® 10 device. Intel® UPI links are DC coupled and don't require AC coupling capacitors.
Symbol/Description Condition Min Typ Max Unit
Supported I/O standards High Speed Differential I/O
Differential on-chip termination resistors PCIe 80 120
Differential peak-to-peak voltage for full swing PCIe 2.5 GT/s 800 1,100 mV
PCIe 5.0 GT/s 800 1,100 mV
PCIe 8.0 GT/s 800 1,100 mV
PCIe 16.0 GT/s 800 1,100 mV
Differential peak-to-peak voltage during EIEOS PCIe 8.0 GT/s and 16.0 GT/s 250 mV
Lane-to-lane output skew PCIe 2.5 GT/s 2.5 ns
PCIe 5.0 GT/s 2 ns
PCIe 8.0 GT/s 1.5 ns
PCIe 16.0 GT/s 1.25 ns
Intel® UPI 133 5 UI
133 Delay of any of Intel® UPI 20 data lanes relative to other data lanes.

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